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Design of Sram Architecture with Low Power without Affecting Speed Using Finfet Cover

Design of Sram Architecture with Low Power without Affecting Speed Using Finfet

International Journal on Smart Sensing and Intelligent Systems
Volume 10 (2017): Issue 5 (January 2017)
By: S. Mohammed Sulaiman,  B. Jaison,  M. Anto Bennet,  M. Vijay,  V. Pandi Selvam and  P. Anandakumar  
Open Access
|Sep 2017

Authors

S. Mohammed Sulaiman

bennetmab@gmail.com

Faculty of Electronics and Communication Engineering, Vel Tech, chennai, INDIA

B. Jaison

Faculty of Computer Science& Engineering,, RMK Engineering College, Chennai, INDIA

M. Anto Bennet

Faculty of Electronics and Communication Engineering, Vel Tech, chennai, INDIA

M. Vijay

UG Student of Electronics and Communication Engineering, Vel Tech, Chennai, INDIA

V. Pandi Selvam

UG Student of Electronics and Communication Engineering, Vel Tech, Chennai, INDIA

P. Anandakumar

UG Student of Electronics and Communication Engineering, Vel Tech, Chennai, INDIA
DOI: https://doi.org/10.21307/ijssis-2017-253 | Journal eISSN: 1178-5608
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Language: English
Page range: 295 - 310
Submitted on: May 27, 2017
Accepted on: Jun 15, 2017
Published on: Sep 1, 2017
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
Static random access memory (SRAM),
Low voltage operation,
Low power consumption
Related subjects:
Engineering,
Introductions and overviews,
Engineering, other

© 2017 S. Mohammed Sulaiman, B. Jaison, M. Anto Bennet, M. Vijay, V. Pandi Selvam, P. Anandakumar, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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