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Design of Low Power Carry Skip Adder Using Dtcmos Cover

Abstract

In the domain of VLSI design, the adders are always meant to be the most fundamental requirements for processors of high performance and other multicore devices. It is found that power dissipation is a major problem in the electronic devices. Power management integrated circuit (PMIC) is emphasized as battery-powered portable electronics such as smart phone are commonly used. In this paper we are designing a carry skip adder which consumes less power than the other conventional adders using dynamic threshold complementary metal oxide semiconductor (DTCMOS).Tthe circuit is designed using tanner EDA simulator of 32nm technology. Also the circuit is compared with the CMOS technology methods.

Language: English
Page range: 284 - 294
Submitted on: May 27, 2017
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Accepted on: Jun 15, 2017
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Published on: Sep 1, 2017
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year

© 2017 T.R. Dinesh Kumar, K. Mohana Sundaram, M. Anto Bennet, R. Aruna, B. Meena, M. Mohanapriya, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.