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Implementation of data cache block (DCB) in shared processor using field-programmable gate array (FPGA) Cover

Implementation of data cache block (DCB) in shared processor using field-programmable gate array (FPGA)

Journal of the National Science Foundation of Sri Lanka
Volume 48 (2020): Issue 4
By:  and    
Open Access
|Dec 2020
Authors

Authors

R. Karthick

karthickkiwi@gmail.com

Sethu Institute of Technology

P. Meenalochini

karthickkiwi@gmail.com

Department of Electrical and Electronics Engineering
DOI: https://doi.org/10.4038/jnsfsr.v48i4.10340 | Journal eISSN: 2362-0161
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Language: English
Page range: 475 - 479
Published on: Dec 31, 2020
Published by: National Science Foundation of Sri Lanka
In partnership with: Paradigm Publishing Services
Keywords:
Dynamic Reconfiguration,
MPSoC,
Multiprocessor

© 2020 R. Karthick, P. Meenalochini, published by National Science Foundation of Sri Lanka
This work is licensed under the Creative Commons Attribution-NoDerivatives 4.0 License.

Volume 48 (2020): Issue 4
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