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Integrating runtime validation and hardware-in-the-loop (HiL) testing with V & V in complex hybrid systems Cover

Integrating runtime validation and hardware-in-the-loop (HiL) testing with V & V in complex hybrid systems

Journal of the National Science Foundation of Sri Lanka

Volume 47 (2019): Issue 4

By: S.D. Dewasurendra, A.C. Vidanapathirana and S.G. Abeyratne

Open Access

|Jan 2020

Authors

S.D. Dewasurendra

devapriyad@pdn.ac.lk

University of Peradeniya

A.C. Vidanapathirana

devapriyad@pdn.ac.lk

Industrial Service Bureau (ISB), Kurunegala

S.G. Abeyratne

devapriyad@pdn.ac.lk

University of Peradeniya

Articles in this issue

DOI: https://doi.org/10.4038/jnsfsr.v47i4.9678 | Journal eISSN: 2362-0161

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Language: English

Page range: 393 - 408

Published on: Jan 25, 2020

Published by: National Science Foundation of Sri Lanka

In partnership with: Paradigm Publishing Services

Keywords:

Complex hybrid systems,

compositional testing,

compositional verification,

hardware-in-the-loop testing,

runtime validation,

V&V – testing integration

© 2020 S.D. Dewasurendra, A.C. Vidanapathirana, S.G. Abeyratne, published by National Science Foundation of Sri Lanka
This work is licensed under the Creative Commons License.

Volume 47 (2019): Issue 4

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