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Performance evaluation of multipliers in reconfigurable hardware Cover

Performance evaluation of multipliers in reconfigurable hardware

Journal of the National Science Foundation of Sri Lanka
Volume 36 (2008): Issue 3
By: ,   and    
Open Access
|Sep 2008
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DOI: https://doi.org/10.4038/jnsfsr.v36i3.160 | Journal eISSN: 2362-0161
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Language: English
Page range: 235 - 237
Published on: Sep 29, 2008
Published by: National Science Foundation of Sri Lanka
In partnership with: Paradigm Publishing Services
Keywords:
FPGA,
Multiplier hardware architecture,
reconfigurable computing,
VHDL

© 2008 WAS Wijesinghe, MK Jayananda, DUJ Sonnadara, published by National Science Foundation of Sri Lanka
This work is licensed under the Creative Commons License.

Volume 36 (2008): Issue 3
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