References
- Adamski, M. and Barkalov, A. (2006). Architectural and Sequential Synthesis of Digital Devices, University of Zielona Góra Press, Zielona Góra.
- Baranov, S. I. (1994). Logic Synthesis for Control Automata, Kluwer Academic Publishers, Boston, MA.
- Barkalov, A. and Titarenko, L. (2009). Logic Synthesis for FSM-Based Control Units, Springer-Verlag, Berlin.
- Barkalov, A., Wegrzyn, M. and Wiśniewski, R. (2006). Optimization of LUT-elements amount in cotrol unit of system-on-chip, Discrete-Event System Design, DESDes '06: A Proceedings Volume from the 3rd IFAC Workshop, Rydzyna, Poland, pp. 143-146.
- Barkalov A., Titarenko L. and Chmielewski S. (2007). Reduction in the number of PAL macrocells in the circuit of a Moore FSM, International Journal of Applied Mathematics and Computer Science17(4): 565-675, DOI: 10.2478/v10006-007-0046-8.
- Brown, S. and Vranesic, Z. (2000). Fundamentals of Digital Logic with VHDL Design, McGraw Hill, New York, NY.
- Bukowiec, A. (2009). Synthesis of Finite State Machines for FPGA Devices Based on Architectural Decomposition, University of Zielona Góra Press, Zielona Góra.
- De Micheli, G. (1994). Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York, NY.
- Gajski, D. (1996). Principles of Digital Design, Prentice Hall, Upper Saddle River, NJ.
- Garcia-Vargas, I., Senhadji-Navarro, R., Jimenez-Moreno, G., Civit-Balcells, A. and Guerra-Gutierrez, P. (2007). ROM-based finite state machine implementation in low cost FPGAs, IEEE International Symposium on Industrial Electronics (ISIE), Vigo, Spain, pp. 2342-2347.
- Kania, D. (2004). The Logic Synthesis for the PAL-based Complex Programmable Logic Devices, Lecture Notes of the Silesian University of Technology, Gliwice, (in Polish).
- Lee, J.M. (1999). VERILOG QuickStart: A Practical Guide to Simulation and Synthesis in VERILOG, Kluwer Academic Publishers, Norwell, MA.
- Łuba, T. (2005). Synthesis of Logic Devices, Warsaw University of Technology Press, Warsaw, (in Polish).
- Łuba, T., Borowik, G. and Kraśniewski, A. (2009). Synthesis of finite state machines for implementation with programmable structures, Electronics and Telecommunications Quarterly55(2): 183-200.
- Maxfield, C. (2004). The Design Warrior's Guide to FPGAs, Academic Press, Inc., Orlando, FL.
- Sentovich, E.M. (1993). Sequential Circuit Synthesis at the Gate Level, Ph.D. thesis, University of California, Berkeley, CA.
- Thomas, D. and Moorby, P. (2002). The Verilog Hardware Description Language, 5th Edn., Kluwer Academic Publishers, Norwell, MA.
- Wiśniewska, M., Wiśniewski, R. and Adamski, M. (2007). Usage of hypergraph theory in decomposition of concurrent automata, Pomiary, Automatyka, Kontrola (7): 66-68.
- Wiśniewski, R. (2005). Partial reconfigutration of microprogrammed controllers implemented in FPGAs, Proceedings of the International Ph.D. Workshop OWD 2005, Wisła, Poland, Vol. 21, pp. 239-242, (in Polish).
- Wiśniewski, R. (2009). Synthesis of Compositional Microprogram Control Units for Programmable Devices, University of Zielona Góra Press, Zielona Góra.
- Wiśniewski, R., Barkalov, A. and Titarenko, L. (2006). Optimization of address circuit of compositional microprogram unit, Proceedings of the IEEE East-West Design & Test Workshop, EWDTW '06, Sochi, Russia, pp. 167-170.
- Zwolinski, M. (2000). Digital System Design with VHDL, Addison-Wesley Longman Publishing Co., Inc., Boston, MA.