Synthesis of finite state machines for CPLDs
By: Robert Czerwiński and Dariusz Kania
Open Access
|Dec 2009References
- Baranov, S. (1994)., Kluwer Academic Publishers, Dordrecht.
- Barkalov, A., Titarenko, L. and Chmielewski, S. (2007). Reduction in the number of PAL macrocells in the circuit of a Moore FSM,(4): 565-575.
- Chattopadhyay, S. (2001). Low power state assignment and flipflop selection for finite state machine synthesis—A genetic algorithmic approach,(45): 147-151.
- Chyży, M. and Kłosiński, W. (2002). Evolutionary algorithm for state assignment of finite state machines,, pp. 359-362.
- Czerwiński, R. and Kania, D. (2005). State assignment for PAL-based CPLDs,, IEEE Computer Society Press, Porto, pp. 127-134.
- Czerwiński, R., Kania, D. and Kulisz, J. (2006). FSMs state encoding targeting at logic level minimization,(4): 479-487.
- Czerwiński, R. and Kulisz, J. (2009). State machine description oriented towards effective usage of vendor-independent synthesis tool,, pp. 27-32.
- Czerwiński, R. (2006)., Ph.D. thesis, Silesian University of Technology, Gliwice, (in Polish).
- De Micheli, G. (1994)., McGraw-Hill Inc., New York, NY.
- Devadas, S. and Newton, A. R. (1991). Exact algorithms for output encoding, state assignment and four-level boolean minimization,(1): 13-27.
- Jóźwiak, L. and Volf, F. (1995). Efficient decomposition of assigned sequential machines and boolean functions for PLD implementations,, pp. 258-266.
- Kania, D. (2003). An efficient approach to synthesis of multi-output boolean functions on PAL-based devices,(3): 143-149.
- Kania, D. (2004)., Silesian University of Technology, Gliwice, (in Polish).
- MCNC (1991). LGSynth'91 benchmarks, Collaborative Benchmarking Laboratory, Department of Computer Science at North Carolina State University, Raleigh, NC
- Mengibar, L., Entrena, L., M.G. Lorenz and E.S. Millan (2005). Patitioned state encoding for low power in FPGAs,(17): 948-949.
- Park, S., Yang, S. and Cho, S. (2000). Optimal state assignment technique for partial scan designs,(18): 1527-1529.
- Salauyou, V., Klimowicz, A., Grzes, T., Dimitrova-Grekow, T. and Bulatowa, I. (2006). Experimental Studies of Finite State Machines Synthesis Methods Implemented in Package ZUBR,(6 bis): 44-46, (in Polish).
- Sentovich, E., Singh, K., Moon, C., Savoj, H., Brayton, R. and Sangiovanni-Vincentelli, A. (1992). SIS: A system for sequential circuit synthesis,, University of California, Berkeley, CA.
- Sharma, K. (1998)., McGraw-Hill, New York, NY.
- Villa, T., Kam, T., Brayton, R. and Sangiovanni-Vincentelli, A. (1997)., Kluwer Academic Publishers, Boston, MA.
- Villa, T. and Sangiovanni-Vincentelli, A. (1990). NOVA: State assignment for finite state machines for optimal two-level logic implementation,(9): 905-924.
- Yang, S. and Ciesielski, M. (1991). Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization,(1): 4-12.
Language: English
Page range: 647 - 659
Published on: Dec 31, 2009
Published by: University of Zielona Góra
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year
Keywords:
Related subjects:
© 2009 Robert Czerwiński, Dariusz Kania, published by University of Zielona Góra
This work is licensed under the Creative Commons License.