Since Peter Shor [1,2] proposed a probabilistic polynomial-time quantum algorithm for integer factorization in 1997, it has inspired many physicists and computer science researchers and has even sparked debates on the possibility of using quantum computing to solve NP-Complete problems. The research on quantum computer and quantum algorithm designs has thus become increasingly popular. The two major features of quantum mechanics are superposition and entanglement. Regarding the quantum superposition property, we can excite multiple quantum bits simultaneously to generate superposition states, thereby expressing various combinations of states, which is akin to generating all possible solutions while solving the optimization problem. However, the difficulty of designing quantum algorithms has also increased significantly compared to traditional algorithms due to the inability to measure the quantum states and their amplitudes during the middle stage of algorithm computation since they will collapse their states after measurement. Another feature, quantum entanglement, allows two entangled quantum particles to maintain their state dependency instantaneously, regardless of the distance between them, giving rise to the new era of quantum communication. This has led to the idea of building a Quantum Internet for the future. The above quantum characteristics open different fashions of methodological development, especially for the quantum algorithm design. One can reference to the quantum computing introduction articles [3–5] for most fundamental concepts of quantum computing.
Nowadays, the design of quantum algorithms is divided into two categories: the quantum-logic algorithm design approach [1, 2, 4, 6–11] and the quantum QUBO algorithm design approach [12–17]. Due to the fact that the general-purpose quantum computer is quite primitive and the available number of qubits is generally limited (the IBM company releases its first ever 1,000-qubit quantum chip in 2023), a middle product called the Quantum Ising Machine that is capable of solving optimization problems [13]. The Quantum Ising Machine is a special-purpose quantum computer that performs a quantum annealing algorithm for solving QUBO (Quadratic Unconstraint Binary Optimization) problem. In the case of an optimization problem that can be transformed to a QUBO form, then it can be executed on the Quantum Ising machine (the D-Wave, Toshiba, and Compal Electronics are promising companies that are developing Quantum Quantum Ising machines (or Digital Quantum Ising Machines)). And many applications, such as drug development, scheduling, supply chain, traffic management, etc., have been applied by the quantum QUBO algorithm design approach to solve the optimization problems [15–17]. Literature [12–14] gave a good introduction to this approach. However, the quantum QUBO algorithm design approach only limits the applications to the optimization problem that can be transformed into a QUBO form. For problems that cannot be transformed into the QUBO form, then the quantum Ising machine is not applicable. Thus, quantum-logic algorithm design is the most fundamental approach since these algorithms are designed using existing quantum logic gates (such as the CNOT gate, CCNOT gate, Hadamard gate, NOT gate, etc., [5]) to compose the quantum circuit to perform the computation steps. This approach has fewer limitations compared to the quantum QUBO algorithm design approach. Thus, we will design our proposed algorithm using this approach. Though the quantum-logic algorithm design is the most extensive approach, the design techniques are quite different from the algorithm design in the traditional Von Neumann architecture computer. However, to date, many algorithm designers have been hesitant to adopt the quantum circuit design approach due to unfamiliarity and the high entry barrier associated with current design methodologies. To provide a simplified and accessible framework for algorithm designers could significantly alleviate the current shortage of quantum-logic algorithms. Due to the above reasons, we will introduce a design framework and give the theoretical proofs for some techniques used in the framework for the quantum-logic algorithm design approach. And we will use the CDS as an example to illustrate the applicability of the proposed framework in the later discussions.
The connected dominating set (CDS) problem is defined as follows: A CDS of a graph G = (V, E) is a subset D of V (D ⊆ V), such that, (1) every vertex in V either belongs to D or is adjacent to a vertex in D; (2) D induces a connected subgraph of G. The CDS problem aims to find the smallest cardinality among all CDS in G. The CDS problem is known to be an NP-hard problem [18] and many real world applications adopt the solution for the CDS problem as the core set for message relaying in Wireless Sensor Networks [19–23], scheduling for industrial engineering [24], and key generation for encryption [25], etc. The routing for mobile ad-hoc networks or wireless sensor networks is generally challenging. For mobile ad-hoc networks, the network nodes will move frequently, causing the network topology to change dynamically. The CDS will generally play a relatively stable backbone network for message replaying. On the other hand, the nodes in a wireless sensor network are generally equipped with limited battery power. Thus, the CDS will also be a good choice for serving the message relaying route to the sink (see Figure 1). Based on the above-discussed applications for the CDS problem, we believe it is worth proposing a quantum-logic algorithm for solving the CDS problem and also using the proposed design framework to illustrate the solution steps. Literature [10] proposed a biomolecular-inspired quantum algorithm for solving the minimum dominating set problem, which is the close related work for this research. However, the considered problem is different to our research, and the solution approach is also different. The study in [26] presents an efficient implementation of Grover’s algorithm for solving the Dominating Set Problem through oracle construction. However, their method does not provide a higher probability of measuring smaller dominating sets. In this work, we address the connected version of the problem. Our contribution is not merely a single solution but rather a framework that systematically constructs quantum circuits for solving graph-theoretic problems. Notably, our approach employs non-uniform initial qubit amplitudes, which effectively enhance the likelihood of measuring smaller connected dominating sets.

The backbone routing for wireless sensor networks using the connected dominating set.
The main objectives and contributions of our work are as follows. First, the paper proposes a quantum algorithm design framework intended to help researchers with backgrounds in electrical engineering and computer science transition more smoothly from classical algorithmic design thinking to quantum algorithm design. The framework also incorporates Grover’s search method and employs a non-uniform amplitude initialization strategy to accelerate the search for solutions. Second, the framework integrates commonly used techniques in quantum algorithm design, such as qubit value updates. We also provided rigorous mathematical proofs to ensure their correctness. Additionally, the non-uniform amplitude input for Grover’s search is supported by corresponding theoretical validations to ensure performance enhancement. Finally, the paper demonstrates the practical applicability of the proposed approach through the Connected Dominating Set Problem, a representative and widely used problem in graph algorithms, especially relevant in network routing applications.
The organization of this article is as follows: Some basic concepts for quantum computing, the proposed quantumlogic algorithm design framework with accelerated search, and some theoretical proof for the design techniques, will be first introduced in next section. The quantum algorithm and circuit for solving the CDS problem using the proposed quantum algorithmic designed framework and the Grover’s search speedup will be illustrated in Section 3 and Section 4, respectively. A simulation result for running the proposed quantum circuit using a numerical example will be demonstrated in Section 5. The concluding remarks will be addressed in the last section.
The quantum mechanism can adopt the photon polarization state to represent values of 0, 1, or more information during the quantum computing process. Generally, the state can be virtually modeled as a unit vector of the Hilbert space. As shown in Figure 2, |φ >= a · |0> + b · |1> can be regarded as the combination of states |0> and |1>, where values a and b represent the amplitude of the |0 > and |1 > states, respectively. The values |a|2 (and |b|2) also stands for the probability of the occurring of states |0 > (and |1 >), respectively. Thus, |a|2 + |b|2 = 1. If a = 1 and b = 0 (by letting θ = 0), it indicates that the quantum state only exhibits the state |0>, and conversely, if a = 0 and b = 1 (by letting θ = π/2), it signifies that the quantum state only exhibits the state |1>. For the special case of letting θ = π/4, then

The fundamental concept for quantum states.
For ease of representation, quantum mechanism expresses states and operations generally using matrices. For example, the Hardamard gate (H), which generates quantum superposition states, operates on state |0 > (vector (1, 0)T representing state |0> and vector (0, 1)T represents state |1>) as follows:
In the existing developed quantum logic gates, one primary constraint is imposed by the unitary properties. The unitary of a matrix U, which corresponding to a quantum logic gate, is that the conjugate transpose matrix U* is its inverse matrix of U; that is, U*U = UU* = I. Basing on this special requirement, the number of currently developed quantum logic gates is limited, which increase the difficulty of quantum algorithm design.
In the following, we will try to stand on a computer scientist point of view to describe the proposed framework while designing a quantum-logic algorithm using an algorithmic approach.
For solving an optimization problem, the brute-force method is traditionally used to find the optimal solution by enumerating all the states of the solution space. The superposition property of qubits fits the need to enumerate all possible states of a solution space. For example, as shown in Figure 3(a), the CDS problem in graph G = (V,E) aims to find the minimum size of a connected dominating set D. Thus, the solution space of the considered problem is equal to the collection of all possible subsets of V. For the state enumeration, we use six qubits |vi>, 0 ≤ i ≤ 5 to represent the vertex selection (or not selection) into a solution. Figure 3(b) shows one of the candidate connected dominating sets ({v1, v4}). In this case, the 6 qubit states are |v1 >= |v4 >= |1> and |v0 >= |v2 > = |v3 >= |v5 >= |0>. For ease of discussion, we will use vi and |vi> interchangeably to represent the state of a qubit for later discussions. Note that one can adopt the Hardamard gate to apply to each qubit with an initial state of |0> to generate the entire solution space in one quantum operation step (see Figure 3(c)). And we use

A numerical example of a CDS problem.
In a graph optimization problem, there will generally be a cost function associated with the vertex set (or the edge set). For example, the vertex cost function values are shown in Figure 4(a). Now one can apply the Pauli-y quantum gate to each qubit to represent the required cost function value on the amplitude of the qubit by the given proper angle θ. Let the cost value that is associated with vertex vi be ci, 0 ≤ i ≤ |V| − 1. Let the angle be

A numerical example for cost function representation.
Generally, the difficult of quantum algorithm design is due to measure the states of quantum bits will cause the states to collapse, and then no more quantum process execution can be done on these quantum bits. In the traditionary algorithm design behavior for the Von Neumann computer, one can easily performe some characteristic determination by Boolean Algebra operations (i.e., using AND, OR, and NOT gates to perform computation for the Disjunctive Normal Form (DNF) formula (or Conjunction Normal Form (CNF) formula). However, the computation for the characteristic determination in quantum computing needs some adjustments.
Firstly, the AND and OR quantum operations (see Figure 5(c)) can be accomplished using the NOT, CNOT, and CCNOT (the so-called Toffoli gate) quantum gates (see Figure 5(a)). Note that the intrinsic of the CNOT series of quantum gates (the CNOT, CCNOT, CCCNOT, etc.) is that if the input value of the target line is |0> (or |1>), then the result of the target line will be equal to the AND (or NAND) operations made on the values of all control lines (see Figure 5(b)). One can easily check and conclude that, if the value of the control lies is all equal to |1 >, then the target line will flip the input value (no matter whether the input value is |0> or |1> on the target line). In the rest of this article, for convention, we will regard the results of applying the CNOT series of quantum gates as the determination of the flip (or not flip) of the input value on the target line.

The AND and OR quantum operations.
Though the AND and OR quantum operations can be implemented for quantum operations, one auxiliary flag qubit is required to store the operation result. This kind of flag qubit is generally used to store the computation results of the characteristic determinations. However, in case one would like to update a property determination in one qubit, then a technique is required to perform this task as follows. And we also try to give the technique a theoretical proof as follows.
To generalize this technique, we assume the required task for performing the value update of the formula x = x + P1 + P2 + … + Pn, where x denotes a quantum bit and Pi, 1 ≤ i ≤ n is the boolean condition determination, i.e., the result for each Pi, 1 ≤ i ≤ n is either true/false (0/1). The operator + denotes the OR operation. Note that, Pi, 1 ≤ i ≤ n may represent the true/false results for the quantum operations that are performed in prior. For ease of illustration, we use the case of n = 2 as an example (i.e., the boolean formula is x + P1 + P2. Since this formula computation would like to keep the result in the qubit x. Thus, the traditional quantum OR and AND operations that shown in Figure 5 no longer fit. To achieve this objective, two steps are performed as follows: At first, the original boolean formula needs to be transformed to its equivalent form by x + (1 − x) · P1 + (1 − x) · (1−P1) · P2, where operator · stands for the AND operation. Then, the equivalent form can be implemented using the CNOT, CCNOT, CCCNOT, … quantum gates (see Figure 6). We called the above implementation the qubit formula update. And to shorten the representation length, we will use

An example for the qubit formula update.
The boolean formula x + P1 + P2 + … + Pn−2 + Pn−1 + Pn and the formula
Since,
Then apply the above result iteratively on each term of Pn−1, Pn−2, …, P2, P1, we have that,
Hence the lemma. Q.E.D.
The boolean formula x + P1 + P2 + … + Pn−2 + Pn−1 + Pn and the transformed formula
Applying the result of Lemma 1 iteratively on each term of Pn, Pn−1, Pn−2, …, P1, then we have that,
Hence the lemma. Q.E.D.
At last, we will try to show that the implementation for the qubit formula update will correctly determine the result of the given boolean formula. By Lemma 2, the original boolean formula x + P1 + P2 + … + Pn is equivalent to the transformed formula
The qubit formula update can correctly implement the original boolean formula x + P1 + P2 + … + Pn, for any given true/false values of Pi, 1 ≤ i ≤ n, where + denotes the OR operation.
At first, by Lemma 2, we can focus on the implementation of the transformed boolean formula, since it is equivalent to the original boolean formula. Let the collection of all possible input values for x, P1, P2, …, and Pn be S* (i.e., S* = {0, 1}n+1). Let the collection of input values data set that can enable quantum circuit Qi, 1 ≤ i ≤ n to flip the results of qubit x be Si. Since QCi is designed for implementing the boolean formula subpart
Now we will check the transformed formula results by given the input data that comes from set Si, 0 ≤ i ≤ n + 1, and to see whether or not it is equal to the final results of the qubit x. For the case of the input values (x, P1, P2, …, Pn) ∈ S0, then the result for the transformed formula will be equal to 1, and none of the quantum circuits will flip the initial input value of x = 1. Thus, the final result of the qubit x will be 1. For the case of the input values (x, P1, P2, …, Pn) ∈ Si, for any i ∈ {1, 2, …, n}, by definition, since
Now, we will give a numerical example to illustrate the application of this technique. Figure 7(a) gives a single edge graph, that is, G = (V, E) = ({vi, vj}, {eij}). In case one wants to determine whether or not a message can be obtained by vertex vj. Two vertex qubits vi and vj are used to represent the status of whether or not a message can be obtained by vertices vi and vj, respectively. A qubit eij is used to represent the existence of edge eij. Then the case of vertex vj will obtain the message that are basing on either one of the following two conditions is met: (1) vertex vj is already having the message (that is vj = 1) or; (2) vertex vj’s neighbor vi is having the message (that is vi = 1 and eij = 1). Thus, the boolean formula for updating vj is vj = vj + vieij. By the above proposed technique, we have the transformed formula

A numerical example for characteristic determination.
Generally, a loop process is frequently used for traditional algorithm design, but it is not provided in quantumlogic algorithm design. Thus, replication is generally a simple technique to implement a loop process. That is, in case a quantum circuit process QC needs to be performed k times, the simplest way is to replicate QC for k times and then synthesize these k quantum circuits QC in sequential order.
For solving the combinatorial optimization problem, after generating the entire solution space using the superposition characteristic on the decision variable set (see Figure 8). One may design several quantum circuits (say QC1, QC2, …, QCk) to perform some characteristic determination processes one by one sequentially to obtain the minimum (or maximum) object function values. However, the main objective is to known which solution will result in the optimum solution value. Therefore, the unitary characteristic (that is, U*U = UU* = I) of the quantum circuit can reverse the operation to obtain the original decision variable values (that is, the optimum solution). Thus, the right part of the quantum circuit in Figure 8 can achieve this objective.

An example for results output and the measurement.
The quantum circuit we designed can also act as an oracle to speed up the search. The oracle encodes the problem structure so that it can mark which states are valid solutions and which are not. For example, if the input qubit state represents a subset of vertices, the oracle checks whether this subset is a connected dominating set (CDS). If the input is a superposition of all possible subsets, then Grover’s algorithm can be applied to find a CDS with a quadratic speedup of
In addition, the initial amplitudes of the superposition can be adjusted so that smaller CDSs have a higher probability of being measured. After running Grover’s iterations, the algorithm is therefore more likely to output a smaller CDS. In this way, the oracle not only reduces the search complexity compared to classical methods, but also helps direct the quantum search toward the most desirable solutions.
The complete architecture for the proposed method to solve the CDS problem is shown in Figure 9. As shown, the proposed method is composed of the following 5 processes sequentially: the state enumeration, the dominating test process, the connected test process, the size computation process, and the results output & measurement. In the following, we will illustrate these processes in detail using the algorithmic description approach.

The architecture of the proposed solution method.
In this process, the graph input and the state space generation follow the above-mentioned technique. Therefore, given a graph topology G = (V, E) for the considered problem, we use qubits |φedge >= ⊗eij∈E|eij = 1> to denote the resulting graph topology, and let qubits |φvertex > to represent the vertex set. We then apply the Hardamard gate to each vertex qubit with an initial value of 0, to obtain the entire solution space of the considered problem; that is,
In this process, we add |V| auxiliary qubits

The solution method for the dominating test process (the dominated flag qubits updating operations).

The solution method for the dominating test process (the dominating test qubit characteristic determination operations).
Now, we need to determine whether this solution is a dominating set or not, and store the result into the characteristic determination qubit |φdominated = 0>. Note that if all of the dominated flag qubits
In this process, the operations of the quantum circuit (QC3) will determine whether a candidate solution (|φvertex>) is connected or not, and then it stores the true/false result into the quantum bit |φconnected >. At first, we propose a subprocess called Reachability testing to test whether or not all of the vertices in the candidate solution are reachable from a given seed vertex vk ∈ V and the true/false result will be stored in an auxiliary qubit NOT-passk. Note that if the seed vertex vk ∈ V belongs to the candidate solution, then the Reachability testing is an effective operation. If the resulting auxiliary qubit NOT-passk = 0 (or 1), then it means the candidate solution is connected (or disconnected). On the contrary, if the seed vertex vk ∈ V does not belong to the candidate solution, then the Reachability testing is an ineffective process, and the resulting auxiliary qubit will obtain NOT-passk = 1. Since one cannot guarantee that the planting seed vertex belongs to the candidate solution, the Connected test process will invoke the Reachability testing for n(= |V|) times and one for letting any vertex vk ∈ V as a seed vertex. In case the auxiliary qubits NOT-passk, vk ∈ V returns a value of 0, then we can conclude that the candidate solution is connected; otherwise, it is disconnected.
The main operations for the subprocess Reachability testing are as follows: A reachable flag qubit

The solution method for the Connected test process (the reachable flag qubit updating operations).
Before performing the Reachability testing subprocess, we will set the reachable flag qubits

The quantum operations for the Connected test process (the Reachability test operations (
The above expanding operation will let the seed of the initial reachable flag value propagate as much as it can. If a seed is planted into a vertex that belongs to the candidate solution vertex set and the solution set is connected, then both of the qubit values of vi and

The quantum operations for the Connected test process (the Reachability test operations (

The operation steps for the Reachability testing process.
Now we will illustrate the complete operations for the Connected test process as follows: Initially, we let the characteristic determination qubit |φconnected > be 0. Since we do not know whether the seed will be planted into a vertex in the candidate solution set or not, a loop will be performed for the seed being planted into each vertex vk ∈ V. When a seed is planted into a vertex vk ∈ V, an auxiliary qubit NOT-passk is used to store the result of this Reachability testing process and we set it to 0 and let

The operation steps for the Connected test process.
The corresponding quantum circuit for the Connected test process is shown in Figure 17. Note that, since the quantum gate operation cannot directly implement the if-then-clause of the seed planted process in Figure 16, we will use the CNOT quantum gate to apply it to the control line qubit vk ∈ V and let the target line be the qubit

The quantum circuit for the Connected test process (QC3).
In this process, the size of a solution set |φvertex > will be determined, and the result will be stored into an auxiliary qubit set |φsize > using the binary numeral system representation. For the example shown in Figure 13, the size of the candidate solution set |φvertex >= |011010 > is equal to 3; thus, |φsize >= |s2s1s0 >= |011 >. Obviously, the number of auxiliary qubits required to store the result is equal to ⌈log2 n⌉ + 1, where n stands for the number of vertices (that is, |V|). In the following, two approaches (the Half adder approach and the Toffoli gate approach) are proposed to achieve the above objective. Detailed descriptions are illustrated using the numerical example of |φvertex >= |v0v1v2v3 > and |φsize >= |s2s1s0>. For any input graph size n can be easily generalized, so we omit it here.
A half adder is quite simple for traditional digital logic. It can add two digits (a and b), and produce a sum bit (S) and a carry bit (C). The carry bit C (and the sum bit S) is equal to the result of performing operations a AND b (and a XOR b), respectively. The quantum circuit with respect to a half adder can be easily implemented (see Figure 18(a)). Now, the main idea for the Half adder approach is to perform the addition for each group of two vertices (say, vi and vi+1), which are shown in the first column of the quantum circuit in Figure 18(b). Note that the carry bits of a half adder are the weight of 21. If we continue to apply a half adder to both of the carry bits of two half adders, the weight of the resulting carry bit will be equal to 22. Following this principle and taking the weight of each output into consideration, the quantum circuit with respect to the Size computation process can then be built. Figure 18(b) gives a quantum circuit (QC4) for a graph with order 4 (that is, |φvertex >= |v0v1v2v3 > and the auxiliary qubits set is |φsize >= |s2s1s0 >). In this numerical example, if |φvertex>= |v0v1v2v3>= |1111>. As shown in Figure 18(b), one can easily check and obtain the result |φsize >= |s2s1s0 >= |100>.

The quantum circuit for the Size computation process (QC4) (the Half adder approach).
This approach first builds a truth table for the size determination results. We use the same numerical example that was used for the Half adder approach (see Figure 19(a)). Then, for each resulting auxiliary qubit, s0, s1, and s2 can be emulated using a series of Toffoli gates (see Figure 19(b)). Detailed descriptions are omitted here.

The quantum circuit for the Size computation process (QC4) (the Toffoli gate approach).
Now, we can apply the quantum-logic algorithm design technique discussed in Section 2 to build the final stage of the quantum circuit for our proposed method. After that, one can start to measure the minimum connected dominating set by giving the following conditions: |φdominated = 1>, |φconnected = 1>, and |φsize = 001> (see Figure 20). Note that if the measure returns that the solution is empty, then the size value can increase by 1 and try to measure the result again until the solution is not empty.

The illustration of the Results output & the measurement.
The circuit proposed in Section 3 can be used to determine whether an input qubit state, representing a vertex subset, is a connected dominating set of a given graph, as illustrated in Figure 9. If the input to the circuit is not a single subset of vertices but rather a superposition of all possible subsets of vertices, we can apply Grover’s search algorithm to find a connected dominating set, achieving a speed-up of
Let the set of all connected dominating sets be S1, S2, …, SM, where each Si is a subset of v1, v2, …, vn and M is the number of solutions. As the primary objective of this paper is to find the minimum connected dominating set, the ideal outcome is one where the measurement probability of obtaining Si is higher than that of Sj if |Si| < |Sj|. In other words, when measuring the result after running Grover’s algorithm with the proposed circuit as the oracle, a smaller CDS is more likely to be obtained than a larger one.
To achieve this objective, the initial superposition is prepared with non-uniform amplitudes. Let n be the number of qubits, N = 2n the dimension of the Hilbert space, and
Let α = [α0 α1 … αN−1]⊤ be the resulting normalized amplitude vector. The initial state |v〉 for the n qubits of the circuit proposed in Section 3 is then prepared as:
By definition, the computational basis
Thus, |v〉 is a properly normalized quantum state (i.e., a unit vector).
For example, let n = 2, so the computational basis is {|00〉, |01〉, |10〉, |11〉}. For each x ∈ {0, 1, 2, 3}, we calculate: s2(0) = 0, so w(0) = 2 − 0 = 2, s2(1) = 1, so w(1) = 2−1 = 1, s2(2) = 1, so w(2) = 2 − 1 = 1, and s2(3) = 2, so w(3) = 2 − 2 = 0. Thus, the weight vector is: w = [2 1 1 0]⊤. The norm is computed as:
The following theorem shows that the state preparation for the weighted amplitudes described above can be implemented by a unitary transformation.
For any normalized state vector |v〉 ∈ ℂN, where N = 2n, there exists a unitary matrix U ∈ ℂN×N such that
Here, |0〉⊗n represents the standard initial state |00…0〉.
Let |v〉 be any normalized vector in ℂN, satisfying 〈v|v〉 = 1. By the Gram–Schmidt orthonormalization process, |v〉 can be extended to a full orthonormal basis of ℂN. That is, there exist vectors |v2〉, …, |vN〉 such that {|v〉, |v2〉, …, |vN〉} is an orthonormal basis of ℂN. We now define the matrix U as U = [|v〉 |v2〉 ⋯ |vN〉], where each |vj〉 is written as a column vector. Since the columns of U form an orthonormal set, it follows that U†U = IN, where IN is the N × N identity matrix. Therefore, U is unitary. Finally, observe that multiplying U by the standard basis vector |0〉 = [1, 0, …, 0]T yields U|0〉 = |v〉, since |0〉 selects the first column of U, which is |v〉 by construction. Thus, such a unitary matrix U exists for any normalized |v〉, as required. Q.E.D.
Based on Theorem 2, for any normalized state vector |v〉 ∈ ℂ2n, there exists a unitary matrix U such that U|0〉 = |v〉. And a method [27] exists to decompose any unitary matrix U into circuits that require
CNOT gates. Therefore, any normalized state |v〉 can be obtained from |0〉 using a circuit that requires
The circuit described in Section 3 is designed to operate on a uniform superposition (i.e., H⊗n|0〉⊗n). However, its functionality remains valid for the non-uniform superposition prepared here. This is due to the principle of linearity in quantum mechanics: the oracle’s logic, implemented with gates like the Toffoli gate, acts on each computational basis state |v〉 independently. The amplitude αv associated with each |v〉 is carried through the transformation unaffected by the logical operations. Therefore, the oracle correctly identifies connected dominating sets regardless of the initial amplitude distribution, allowing our approach to enhance the measurement probability of smaller sets of CDS.
We formalize the circuit from Section 3 as a quantum oracle, denoted by uf. This oracle acts on an input register |v〉 and an ancilla qubit |y〉. It evaluates a function f(v) that determines if the vertex set corresponding to v is a connected dominating set (CDS):
The action of the oracle is defined as a conditional bit-flip on the ancilla qubit:
Then we have
After the oracle uf has marked the solution states by inverting their phase, the next step is to amplify their amplitudes. This is achieved using a weighted reflection operation g = 2|v〉〈v|−IN. By repeatedly applying guf to the initial state |v〉, the amplitudes of the solution states are amplified, allowing a desired CDS to be obtained with high probability upon measurement.
Standard derivations of Grover’s algorithm, such as in [6,7,28], assume a uniform superposition as the initial state:
Recall that our initial state is:

Geometric visualization of the weighted search algorithm in the two-dimensional subspace. The initial state |v〉 makes angle
Oracle uf flips the sign of the amplitude corresponding to |xt〉. That is uf|v〉 = (∑x≠xt αx|x〉) – αxt|xt〉 — applying uf to |v〉 results in the reflection of |v〉 across the horizontal axis. The position of uf|v〉 is illustrated in Figure 21.
Next, we describe the action of the operator g. Let uf|v〉 = |ψ〉. To understand the action of g on |ψ〉, we first decompose |ψ〉 into |ψ〉 = a|v〉 + b|v⊥〉 — the state |ψ〉 can be expressed as a linear combination of the mutually perpendicular states |v〉 and |v⊥〉. Then, the operator g is applied to |ψ〉 producing g|ψ〉 = a|v〉 − b|v⊥〉 because g|v〉 = |v〉 and g|v⊥〉 = (2|v〉 〈v|−IN)|v⊥〉 = 2|v〉 〈v||v〉⊥ − |v⊥〉 = −|v⊥〉 where 〈v|v⊥〉 = 0. This result shows that the component of |ψ〉 parallel to |v〉 is unchanged, while the component orthogonal to |v〉 is inverted. This is precisely the definition of a reflection of the state |ψ〉 across the axis defined by |v〉. The position of guf|v〉 is illustrated in Figure 21.
To summarize the analysis presented above, the application of guf to |v〉 results in a rotation of |v〉 toward |xt〉 by angle θ, with the rotation angle θ increasing as αxt increases. Now, we proceed to determine the required number of iterations of the guf operator and analyze the probability for finding our target state |xt〉.
Since the initial angle between |v〉 and the horizontal axis is
In the Grover’s search, if M (the number of solutions) is unknown, the optimal iteration count k cannot be computed exactly. To handle this, we use an adaptive strategy. The algorithm runs step by step with k adjusted based on measurement results. We begin with an initial guess
Grover operators uf and g can be represented as 2n-dimensional unitary matrices. Based on the previously mentioned method [27], each of them can be implemented using
This section provides an analysis to estimate the difference in the final measurement probability between two solution states whose number of 0 differ by one. This analysis relies on the geometric intuition of the amplitude amplification process derived previously.
A complete mathematical derivation of the probability difference ΔP is hard because we do not know all the required information in advance. To obtain an exact formula such as ΔP = f(n, M, w(x1), w(x2),…), we would need to know how many solutions there are (M) and what the weight of each solution is. Since this information is unavailable, we focus on analyzing one target state at a time. Using simple approximations (for example, θ ≈ 2αxt), we can still understand how the final measurement probability depends on the initial amplitude of a solution.
Let |x1〉 and |x2〉 be two distinct target states (Connected Dominating Sets) corresponding to bitstrings whose number of 1s differ by one:
The state |x1〉 is the preferred solution as it corresponds to a smaller CDS (fewer ones, more zeros). The initial amplitudes are:
This confirms that the preferred solution |x1〉 has a greater initial amplitude: αx1 > αx2.
We adopt the approximations derived from the weighted amplitude amplification (where the angle of rotation θ is approximately 2αxt).
The number of iterations required to optimally amplify the preferred state |x1〉 is:
We run the algorithm for this fixed number of iterations, resulting in the final state |ϕ〉.
The final probability of measuring |x1〉, P(x1), is given by P(x1) = cos2(ϵ1), where ϵ1 is the small angle between |ϕ〉 and |x1〉. When number of iterations is k1, ϵ1 is bounded by
Since αx1 is small for large n, this probability P(x1) is very close to 1.
Each Grover iteration, guf, rotates the state vector by an angle of θ2 towards |x2〉. The algorithm is executed for k1 iterations, where k1 is the number of iterations optimized for the preferred target |x1〉, not for |x2〉. After k1 iterations, the total angle θtotal of the state vector with respect to the horizontal axis is given by the initial angle plus the accumulated rotation:
The quantity of interest is the final angle, ϵ2, between the final state |ϕ〉 and the target axis |x2〉 (which is at angle π/2). This angle is the absolute difference between their final angular positions:
From the analysis for the preferred state |x1〉, we know that the optimal number of iterations is approximately:
We substitute this expression for k1 into the equation for ϵ2:
We now simplify the expression inside the absolute value. First, distribute θ2:
Finally, using the approximation θ ≈ 2α, we can express the angle in terms of the initial amplitudes:
We analyze the ratio αx2/αx1 for the two target states:
Substituting this ratio back into the expression for the final angle ϵ2:
Since w(x1) is large (it is at most n), ϵ2 is a small angle. We utilize the small-angle approximation for the cosine function:
The difference in the final measurement probabilities ΔP is:
To confirm that ΔP > 0, we must show that the first term in Equation 4 is greater than the second term, i.e.,
The left-hand side of this inequality grows exponentially with the number of qubits n (dominated by the 2n term), while the right-hand side grows only polynomially (O(n4)). This condition therefore holds for any reasonably large n, which rigorously confirms that ΔP > 0 and thus P(x1) > P(x2).
Using mathematical induction, one can prove that the inequality remains valid for all n ≥ 6 under the worstcase condition s2(x1) = 0. Since practical graph problems typically involve n well above this threshold, we can confidently conclude that ΔP > 0 for any meaningful problem size.
By selecting the iteration count k1 optimized for the preferred solution |x1〉, the algorithm leverages this initial advantage, resulting in a final probability distribution that significantly favors the smaller CDS |x1〉 over the larger one |x2〉.
We summarize the results of this section with the following theorem.
The minimum connected dominating set (CDS) can be found in
To demonstrate and verify the proposed scheme, we use Qiskit [29], an open-source software framework for quantum computing, to implement the algorithm and test it using the problem instance described in the previous sections.
The problem instance is the graph G = (V, E) where V = {v5, v4, v3, v2, v1, v0} and E = {e01, e12, e14, e23, e34, e45}. In Figure 10, the visual representation of this graph is shown. To demonstrate the impact of graph complexity on solving time, we also tested our proposed method using another graph, G′. Graph G′ is formed by removing edge e14 from graph G. That is, G′ = (V′ = V, E′ = E − {e14}). We used Qiskit to implement the method proposed in this paper to find the smallest connected dominating set on G and G′. The library Qiskit has been adopted as a standard tool by many quantum computers, so our developed programs can be executed on real quantum computers. Given that access to real quantum computers is limited, this paper uses Qiskit’s simulation component, Qiskit Aer, to conduct our experiments. The simulation method used in this paper is matrix_product_state, one of several simulation methods available in Qiskit Aer. The simulation method matrix_product_state, originally proposed by Vidal [30], is further detailed in [31]. All simulation experiments were conducted on a computer running the Ubuntu 22.04 operating system and using an AMD Ryzen 7 3700X 8-core processor. This CPU has a clock speed of 2200 MHz and a cache size of 512 KB.
Next, we describe how to implement the proposed method for finding the connected dominating set of graph G. The circuit for finding the dominating set on G′ is similar to that of G, except for the removal of the components related to edge e14. Six qubits |v〉 = |v5v4v3v2v1v0〉 are used to represent vertices, and six qubits |e01〉, |e12〉, |e14〉, |e23〉, |e34〉, |e45〉 are used to represent edges. Qubits |e01e12e14e23e34e45〉 are initialized to |111111〉. In the initial stage, vi are initialized to |0〉 where 0 ≤ i ≤ 5 and Hadamard gates are used to transform each of the six vertices into a superposition state, allowing the simultaneous execution of the dominating test and the connecting test on all vertex subsets. That is
Now, we are ready to implement the dominating test process. The circuit shown in Figure 22 implements the method mentioned in Section 3.2. For simplicity, we only show QC201 and QC210 in Figure 22. Using the same construction rules as in Figure 22, readers can extend this to obtain QC212, QC221, QC223, QC232, QC234, QC243, QC245, QC254, QC214, and QC241. Notice in Figure 22 that we use aux0 and aux1 to respectively store

QC201 and QC210.
After completing the implementation of the dominating test, we then implemented the connecting test. First, the circuit uses a controlled NOT gate to implement the setting of the value of Process Connected-test, line 4. See the leftmost CNOT in Figure 23 for illustration. Then QC301, QC310, QC312, QC321, QC323, QC332, QC334, QC343, QC345, QC354, QC314, and QC341 are implemented as shown in Figure 23. Note the repeated structure as illustrated in Figure 13. A similar circuit to that shown in Figure 23 will be repeated six times in total, with a different seed

Implementation of QC301, QC310, QC312, QC321, QC323, QC332, QC334, QC343, QC345, QC354, QC314, and QC341.
After completing the connecting test, we implemented two methods to determine the size of the dominating set: one using half-adders and the other using truth tables.
In the truth table approach, we use Toffoli gates to implement the circuit for converting unary to binary representation. See Figure 24 for an illustration of the circuit used to calculate the size of the dominating set. Here, we reuse

Implementation of the truth table approach for finding the size of the dominating set.
In Figure 25, a circuit utilizing several half adders to calculate the size of the dominating set and convert it to a binary representation is implemented. Notice that the maximum dominating set size in this example is 6, which is not exactly a power of 2. As a result, some intermediate results calculated by the half adders will not be used in determining the final result. For example, t16, t19, and t20 can be ignored in this instance. Although t16, t19, and t20 in Figure 25 can be disregarded and some auxiliary qubits can be reused, for the sake of clarity in demonstrating the relationships between the half adders, we present the complete input and output relationships of all the half adders.

The implementation of the half-adder approach for finding the size of the dominating set.
In Figure 26, we compare the difference in computation time caused by using the truth table approach (the fast adder approach) versus the half adder approach, while keeping all other circuits identical. The x-axis represents the number of measurements, and the y-axis represents the computation time required. From the figure, we can observe that as the number of shots increases, the required time increases linearly. Additionally, the time required using the half adder approach remains consistently higher compared to the truth table approach.

Comparison of the simulation time of graph G between using fast adder and half adder. The x-axis is the number of shots in the simulation, and the y-axis represents the simulation time (in seconds).
To demonstrate the impact of different edge counts in the graph, we removed edge e14 from graph G to create graph G′. It is evident that the minimum connected dominating set of G is {v1, v4}, while the minimum connected dominating set of G′ is {v1, v2, v3, v4}. The aforementioned experiments conducted on graph G were also applied to graph G′, and the results are shown in Figure 27. We compared the total computation time required to calculate the connected dominating set and size of the connected dominating set of graph G′ using both the half adder approach and the truth table approach under different numbers of shots. Based on Figure 27, we observe a trend similar to that in Figure 26: as the number of shots increases, the computation time also increases linearly. Additionally, the time required using the truth table approach remains consistently lower than that of the half adder approach. By comparing Figure 26 with Figure 27, we observe that, for the same number of nodes, a lower number of edges results in reduced computational time. This result aligns with theoretical expectations. Although the number of nodes remains unchanged, an increase in the number of edges leads to an increase in the number of sub-circuits in QC2, QC3, and QC4, thereby extending the overall computation path length.

Comparison of the simulation time of graph G′ = (V, E – {e14}) between using fast adder and half adder The x-axis represents the number of shots in the simulation, and the y-axis represents the simulation time (in seconds).
Now, we try to analyze the worst case bound for the number of qubits and the universal quantum gates used in our proposed method. Note that the proposed method consists of 5 processes, namely, the state enumeration, the dominating test process, the connected test process, the size computation process, and the results output & measurement. In the following, we will examine the number of qubits used in each process. Note that, since the process of the results output & measurement takes no auxiliary qubits used, we omit it here.
In this process, the problem instance input takes n qubits for |φvertex> and m qubits for |φedge>, where n (and m) is equal to |V| (and |E|). The total number of qubits used in this process is equal to n + m. And it takes n hadamard gates to generate the solution space in this process.
In this process, the additional auxiliary qubits used in the quantum circuit QC2_a (see Figure 10(b) and Figure 11(a)) are the dominated flag qubit set
In addition, the result will be stored in a characteristic determination qubit |φdominated>, which takes 1 qubit. Summarizing the above discussions, we conclude that the total number of additional auxiliary qubits used for the dominating test process is equal to n + 2 + ⌈(n – 1)/3⌉ + 1 = n + ⌈(n – 1)/3⌉ + 3.
For the analysis of universal quantum gate usage, each Toffoli gate (or CCCCNOT gate) can be implemented using 2 (or 4) CNOT gates. Accordingly, the quantum circuit QC2ij (see Figure 10(b)) requires 8 universal quantum gates. Since the quantum circuit QC2a contains a loop that iterates m times, and each iteration executes both QC2ij and QC2ji, the total number of universal quantum gates required for QC2a is 16m. The quantum circuit QCb shown in Figure 11(b), use 4 auxiliary qubits per group and applies the CCCCNOT gate to generate intermediate results. This process is then applied recursively in a tree-like manner. The total number of universal quantum gates required to implement QC2b can thus be calculated as:
In this process, the additional auxiliary qubits are the connected flag qubit set
For the analysis of universal quantum gate usage in the reachability testing phase, the quantum circuit QC3ij (see Figure 12(b)) requires 5 universal quantum gates. The quantum circuit
In this process, the auxiliary qubits to store the result are |φsize>, which takes ⌈log2 n⌉ + 1 additional qubits. For the Half adder approach (see Figure 18), the additional qubits used are equal to the number of carry bits and sum bits in the first column half adder of the quantum circuit (the other half adders can reuse the auxiliary qubits). Thus, there is a total of n qubits to play the roles of carry bits and sum bits. The total number of additional qubits used in this process (using the Half adder approach) is equal to n + ⌈log2 n⌉ + 1. Similarly, the same arguments can be made on the Toffoli gate approach, and the total number of qubits used in this process is equal to ⌈log2 n⌉ + 1.
For the analysis of universal quantum gate usage in the size computation process, the Toffoli gate approach uses a truth table of size 2n rows to determine each of the size-resulting auxiliary qubits s0, s1, …, s⌈log2 n⌉. For each resulting qubit si, where 1 ≤ i ≤ ⌈log2 n⌉, the implementation depends on the number of 0′s (or 1′s) in the corresponding result column (see Figure 19(b)). In the worst case, this requires 2n−1 Toffoli gates. Since each Toffoli like gate requires n universal quantum gates to implement, the total number of universal quantum gates required in the worst case is n · log2 n · 2n−1. For the alternative Half adder approach, the gates complexity is similar to that of the Toffoli gate approach, and thus it is omitted here for brevity.
Now, summarizing the above discussions and adding the number of qubits used in each process, for the worst case we will have (n + m) + (n + ⌈(n − 1)/3⌉ + 3) + 1 + (n + ⌈log2 n⌉ + 1)= m + 3n + ⌈(n−1)/3⌉ + ⌈log2 n⌉ + 5. The total number of universal quantum gates required for the complete process is given by the sum of
The number of qubits used for performing the proposed method is equal to m + 3n + ⌈(n − 1)/3⌉ + ⌈log2 n⌉ + 5 = O(n + m). In terms of gate complexity, the proposed methods requires O(n·log2 n·2n−1) universal quantum gates.
Before concluding this subsection, we note that quantum computers are still in a very early stage of development compared to conventional computer architectures. As a result, the use of qubits and quantum gates remains a critically scarce resource, making their optimization an essential concern in quantum algorithm design. Since the method proposed in this paper is presented with an emphasis on accessibility for readers, there remains considerable room for improvement in terms of resource efficiency. Below, we propose suggestions for the implementation phase, focusing on principled design decisions. For example, in the dominating test process, during the dominating-test qubit characteristic determination operations (see Figure 11(b)), our original design groups four dominating-test qubits at a time and uses one ancilla qubit to compute a temporary result. These partial results are then combined recursively, layer by layer, until all results are consolidated and written into qubit |φdominated>. According to the computation in Equation (5), this approach requires
From the perspective of universal quantum gate usage, a similar discussion applies. In the design of the dominating test flag computation, when implementing circuit QC2b, the method can be generalized by grouping k qubits at a time (with the current implementation using k = 4, as shown in Figure 11(b)). Under this generalization, the number of universal quantum gates required can be expressed as
In this paper, we first propose a quantum algorithmic circuit design framework aimed at easing the learning curve for algorithm designers entering the field of quantum algorithm development. Based on this framework, we then present a quantum-logic algorithm for solving the Connected Dominating Set (CDS) problem as an example. The proposed solution method adopts a structured algorithmic approach to illustrate the sequence of quantum operations. This paper also discusses several quantum-logic algorithm design techniques from a computer science perspective, forming the foundation of the proposed framework. A correctness proof is provided for one of the core design techniques frequently used in our solution. We extended this with a weighted Grover’s algorithm using non-uniform amplitudes that bias search toward smaller CDSs, achieving quadratic speedup. Unlike standard approaches, our method naturally prioritizes optimal solutions. To verify the proposed method, we implement it for the CDS problem and validate its correctness using a numerical example on IBMs Qiskit quantum simulator. Furthermore, we analyze the number of qubits required by the proposed method. In future work, we suggest the development of additional practical quantum-logic algorithm design techniques to further simplify the quantum algorithm design process for researchers.