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Width Optimization of Quantum Circuit Based on Reuse-Aimed Quantum Circuit Transformation Cover

Width Optimization of Quantum Circuit Based on Reuse-Aimed Quantum Circuit Transformation

Quantum Information & Computation
Volume 25 (2025): Issue 3 (June 2025)
By: Haotian Tang,  Fei Ding,  Xueyun Cheng,  Shuxian Zhao and  Zhijin Guan  
Open Access
|Jul 2025

Figures & Tables

Figure 1.

Reduce qubit of circuit by qubit reuse: (a) Original circuit, (b) Reuse q0 to replace q1.
Reduce qubit of circuit by qubit reuse: (a) Original circuit, (b) Reuse q0 to replace q1.

Figure 2.

Sequential partitioning for circuit: (a) Original circuit, (b) Circuit after sequential partitioning.
Sequential partitioning for circuit: (a) Original circuit, (b) Circuit after sequential partitioning.

Figure 3.

Equivalent circuit after reuse q0 for replacing q1.
Equivalent circuit after reuse q0 for replacing q1.

Figure 4.

Circuit after transformation.
Circuit after transformation.

Figure 5.

Equivalent circuit after reuse q0 for replacing q4.
Equivalent circuit after reuse q0 for replacing q4.

Figure 6.

Preceding gates and succeeding gates of qubit pair (q0, q4) in circuit of Figure 3.
Preceding gates and succeeding gates of qubit pair (q0, q4) in circuit of Figure 3.

Figure 7.

Example of execution process of RaQCT.
Example of execution process of RaQCT.

Figure 8.

Width optimization of quantum circuit based on tree structure: (a) Viewing the circuit width optimization as a process of generating tree nodes, (b) Generating k child nodes by k reusable pairs.
Width optimization of quantum circuit based on tree structure: (a) Viewing the circuit width optimization as a process of generating tree nodes, (b) Generating k child nodes by k reusable pairs.

Figure 9.

Width optimization process of medium or large circuits.
Width optimization process of medium or large circuits.

Figure 10.

The width optimization rate of different regular circuits by methods in [24,26] and our proposed ES and GHS. The labels on the x-axis are the circuit names, with the original width of the circuits in parentheses on the right. The ticks on the y-axis represent the width optimization rate.
The width optimization rate of different regular circuits by methods in [24,26] and our proposed ES and GHS. The labels on the x-axis are the circuit names, with the original width of the circuits in parentheses on the right. The ticks on the y-axis represent the width optimization rate.

Figure 11.

Comparison of average width optimization rate of QAOA circuits.
Comparison of average width optimization rate of QAOA circuits.

Figure 12.

Comparison of time cost between ES and GHS. The labels on the x-axis represent the circuit names, and the original width of each circuit is given in parentheses.
Comparison of time cost between ES and GHS. The labels on the x-axis represent the circuit names, and the original width of each circuit is given in parentheses.
DOI: https://doi.org/10.2478/qic-2025-0011 | Journal eISSN: 3106-0544 | Journal ISSN: 1533-7146
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Language: English
Page range: 216 - 231
Submitted on: Mar 7, 2025
|
Accepted on: Apr 16, 2025
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Published on: Jul 1, 2025
Published by: Cerebration Science Publishing Co., Limited
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
qubit reuse,
mid-circuit measurement and reset,
quantum circuit width optimization,
quantum circuit transformation
Related subjects:
Physics,
Quantum physics,
Mathematics,
Applied mathematics,
Computer sciences,
Computer sciences in the humanities,
Computer sciences,
Computer sciences in natural sciences

© 2025 Haotian Tang, Fei Ding, Xueyun Cheng, Shuxian Zhao, Zhijin Guan, published by Cerebration Science Publishing Co., Limited
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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