Figure 1.
The proposed single-phase 31-level inverter circuit.
Figure 2.
The operation modes of the inverter system illustrate how the switching variables control the voltages: (a) The effect of (x3, x1) combinations on VAA′; (b) The effect of (x4, x2) combinations on VB′B; (c) The effect of x5 on VA′B′.
Figure 3.
Comparison of the reference current with currents predicted by linear and cubic spline extrapolation.
Figure 4.
Flow chart of the FCS-MPC control function. FCS-MPC, finite control set-model predictive control.
Figure 5.
Simulation model of the FCS-MPC controlled 31-level inverter. FCS-MPC, finite control set-model predictive control.
Table 1.
Circuit and 31-level inverter parameters.
| Parameter | Symbol | Value |
|---|---|---|
| Voltage step | E | 100 V |
| The load | R, L | 100 Ω, L = 0.2 H |
| Reference current | 12 sin (100 πt) | |
| Inverter capacitors | C1, C2 | 100 µF |
| MOSFET | Ron, Roff | 0.1 Ω, 100 kΩ |
| Sampling time | Ts | 0.5 ms |
Figure 6.
Variation of capacitor voltage switching losses and current distortion with the weighting factors with one-step prediction horizon. THD, total harmonic distortion.
Table 2.
Optimum weighting factors and the corresponding performance indicator with one-step prediction.
| Variable | Kv | Kc | THD (io) | ∑ Vsw fsw | Vc1,dc | Vc2,dc | |
|---|---|---|---|---|---|---|---|
| Value | 0.7 | 0.22 | 0.00965 | 220 | 0.01643 | 100.1 V | 201.2 V |
Figure 7.
The 31-level inverter operation under the one-step prediction horizon MPC algorithm. The waveforms shown are reference and output current (top), the two capacitor voltages (middle) and the switching state (bottom). MPC, model predictive control.
Figure 8.
The 31-level inverter operation under the two-step prediction horizon MPC algorithm. The waveforms shown are reference and output current (top), the two capacitor voltages (middle) and the switching state (bottom). MPC, model predictive control.
Table 3.
Optimum weighting factors and the corresponding performance with two-step prediction.
| Variable | WSS | Kv | Kc | THD (io) | ∑Vsw fsw | Vc1,dc | Vc2,dc | |
|---|---|---|---|---|---|---|---|---|
| Value | 0.25 | 0.7 | 0.22 | 0.00973 | 223 | 0.0152 | 100.2 V | 201.1 V |
Table 4.
Comparison of the proposed 31 level inverter to other comparable designs.
| [Ref] | Saforo et al. (2020) | Arif et al. (2021) | Panda et al. (2021) | Memon et al. (2024) | Khasim and Dhanamjayulu (2022) | Radhakrishnan et al. (2024) | Proposed |
|---|---|---|---|---|---|---|---|
| NLevels | 17 | 17 | 17 | 13 | 33 | 25 | 31 |
| Ndc | 2 | 1 | 4 | 1 | 4 | 4 | 2 |
| Ndc/NLevels | 0.118 | 0.059 | 0.235 | 0.077 | 0.1212 | 0.16 | 0.064 |
| Ns | 12 | 12 | 10 | 12 | 16 | 13 | 10 |
| 0.706 | 0.706 | 0.588 | 0.923 | 0.485 | 0.52 | 0.322 | |
| Ncap | 4 | 3 | 0 | 3 | 0 | 0 | 2 |
| TSV: ∑ Voff,sw/Vo.max, p | 3.375 | 4.5 | 5 | 4 | 2.9 | - | 2.5 |
| TCV: ∑ Vcap/Vo.max, p | 1 | 0.875 | 0 | 0.833 | 0 | 0 | 0.2 |
| (Max no. of switches in current path)/levels | 4/17 = 0.234 | 6/17 = 0.353 | 5/17 = 0.294 | 5/13 = 0.385 | 7/33 = 0.212 | 6/25 = 0.24 | 5/31 = 0.161 |