Layer-specific parallelization for FPGA-based convolutional neural network accelerators: Performance and resource evaluation

Deep learning (DL) models require significant computational resources, making their deployment on edge devices with limited power and hardware capabilities challenging. Field-programmable gate arrays (FPGAs) provide an effective platform for accelerating such workloads because of their inherent parallelism and energy efficiency. This study investigates the impact of layer-wise parallelization levels, represented by folding coefficients, on the resource utilization and performance of FPGA-based DL accelerators, with a specific focus on convolutional (CONV) and fully connected (FC) layers. A LeNet-based accelerator model was implemented using the Xilinx FINN framework with W1A2 quantization (1-bit weights and 2-bit activations). Three folding coefficients, namely low (L), medium (M), and high (H), were defined for both the CONV and FC layers, yielding nine unique parallelization configurations. These accelerators were deployed on the PYNQ-Z1 platform and evaluated using the Fashion-MNIST dataset. A comprehensive evaluation quantifies key metrics, such as throughput (frames per second, FPS), resource utilization (look-up tables (LUTs), flip-flops (FFs), and block RAMs (BRAMs)), and power consumption. The results show that lower folding levels, corresponding to higher parallelism, significantly enhance the throughput, reaching up to 6809 FPS in the L-M and L-L configurations. This represents a 13-fold improvement over the baseline H-H configuration (C1) at the cost of increased resource usage. This study extends prior research on quantized neural networks (QNNs) by analyzing layer-specific parallelization strategies through adjustable folding factors and their effects on performance and resource trade-offs, offering valuable insights for optimizing FPGA-based deep learning (DL) inference in resource-constrained environments.