The scaling of metal oxide semiconductor field effect transistor (MOSFET) causes many limitations in current scaled technology nodes. The secondary effects limit the application of MOSFETs in nanoscaled logic circuits. Many alternative ways are suggested for the innovation of new technological developments. Quantum-dot cellular automata (QCA) nanotechnology is getting key attention in the current scenario due to the ability of fast, power- and area-efficient implementations of the logic circuits. The exclusive OR (XOR) gate is the basic building block of many logic applications. Hence, this paper proposes an optimized novel structure of a 3-input XOR (XOR3) gate, which is successfully verified for the logic designs of a 4-bit parity generator, a 4-bit full adder, and a 4-bit binary to gray code converter. The proposed XOR3 gate consists of 8 QCA cells only and 2 clock phases. The reliability concern in terms of fault-tolerant analysis for the proposed XOR3 gate is also presented in the paper. The proposed designs are compared with the existing designs and show the improved performance metrics. The QCA Designer-E tool is used for circuit simulations. The energy dissipation values are estimated using the QCA Designer-E and the QCA Pro tools. The proposed XOR3 gate, 4-bit parity generator, 4-bit full adder, and 4-bit binary to gray code converter save a total of 20%, 26.32%, 26.40%, and 17.24% of cells, respectively, in comparison with the best-reported similar design.
© 2025 Vijay Kumar Sharma, published by Slovak University of Technology in Bratislava
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