Design of CMOS low noise amplifier with inductive degeneration for navigation application

Sharma, Abhishek; Kalra, Dheeraj; Kumar, Manish; Bhatia, Rajiv

doi:10.2478/jee-2024-0054

Abstract

This paper presents an advanced Low Noise Amplifier (LNA) tailored for high-precision navigation applications, designed using the 180nm technology node and implemented in Cadence Virtuoso. The LNA features a single-ended amplifier configuration with cascaded NMOS transistors to achieve superior isolation and input matching through source degeneration, optimizing gain and noise performance. At 1.2 GHz, the amplifier achieves a gain of 33 dB and a noise figure of 1.3 dB. It demonstrates a 1 dB compression point of –16 dBm and a third-order intercept point (IIP3) of –10 dBm, with a power consumption of 44 mW from a 1.8 V supply. Post-layout simulations reflect a noise figure of 2.9 dB and a gain of 19.5 dB, highlighting practical design considerations. The layout area is 0.51 mm², underscoring the compact yet highly efficient design.

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Design of CMOS low noise amplifier with inductive degeneration for navigation application

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