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Design and verification of a low-power AC/DC converter Cover

Design and verification of a low-power AC/DC converter

Open Access
|May 2021

Abstract

This paper deals with the development and experimental verification of a low-power AC/DC converter. The proposed solution is aimed at the sub 0.5 W output power domain, commonly encountered in applications such as always-on wireless sensing nodes. To implement the proposed converter topology, a prototype application specific integrated circuit was designed and manufactured in a high voltage 0.35 µm CMOS technology, able to handle the maximum voltage of up to 120 V. The proposed design was first analyzed by transistor-level simulations showing high power efficiency and low no-load consumption of the developed converter. To facilitate experimental verification and measurement, an printed circuit board with the necessary external components was developed, as the available technology is unable to handle the AC line voltage directly. While the developed converter operated well with decreased input AC voltage, reliability issues arose during operation with the full AC line voltage of 230 Vrms. These are linked to digital control circuitry of the implemented chip and could be addressed in the second manufacturing run in the future.

DOI: https://doi.org/10.2478/jee-2021-0015 | Journal eISSN: 1339-309X | Journal ISSN: 1335-3632
Language: English
Page range: 113 - 118
Submitted on: Feb 15, 2021
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Published on: May 12, 2021
In partnership with: Paradigm Publishing Services
Publication frequency: 6 issues per year

© 2021 Miroslav Potočný, Viera Stopjaková, Martin Kováč, published by Slovak University of Technology in Bratislava
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.