Have a personal or library account? Click to login
Multilayer optical interconnects design: switching components and insertion loss reduction approach Cover

Multilayer optical interconnects design: switching components and insertion loss reduction approach

Open Access
|Jul 2018

References

  1. [1] D. A. Miller, “Optical Interconnects to Electronic Chips”, Ap- plied Optics, vol. 49, 2010, pp. F59-F70.10.1364/AO.49.000F5920820203
  2. [2] D. A. Miller, “Rationale and Challenges for Optical Intercon- nects to Electronic Chips”, Proceedings of the IEEE, vol. 88, 2000, pp. 728-749.10.1109/5.867687
  3. [3] I. O’Connor and G. Nicolescu, Integrated Optical Interconnect Architectures for Embedded Systems, Springer Science & Busi- ness Media, 2012.10.1007/978-1-4419-6193-8
  4. [4] C. Gunn, “CMOS photonics for high-speed interconnects”, IEEE Micro, vol. 26, 2006, pp. 58-66.10.1109/MM.2006.32
  5. [5] G. T. Reed, G. Mashanovich, F. Gardes and D. Thomson, “Silicon Optical Modulators”, Nature photonics, vol. 4, 2010, pp. 518-526.10.1038/nphoton.2010.179
  6. [6] A. Liu, R. Jones, L. Liao, D. Samara-Rubio, D. Rubin, O. Cohen et al , “A High-Speed Silicon Optical Modulator based on a Metal-Oxide-Semiconductor Capacitor”, Nature, vol. 427, 2004, pp. 615-618.10.1038/nature0231014961115
  7. [7] Q. Xu, B. Schmidt, S. Pradhan and M. Lipson, “Microme- tre-Scale Silicon Electrooptic Modulator”, Nature, vol. 435, 2005, pp. 325-327.10.1038/nature0356915902253
  8. [8] R. A. Soref and B. R. Bennett, “Electrooptical effects sili- con”, IEEE Journal of Quantum Electronics, vol. 23, 1987, pp. 123-129.10.1109/JQE.1987.1073206
  9. [9] M. Briere, B. Girodias, Y. Bouchebaba, G. Nicolescu, F. Mieye- ville, F. Gaffiot et al , “System Level Assessment of an Optical NoC an MPSoC Platform”, Proceedings of the conference on design, automation and test, Europe, 2007, pp. 1084-1089.10.1109/DATE.2007.364438
  10. [10] X. Tan, M. Yang, L. Zhang, Y. Jiang and J. Yang, “A Generic Optical Router Design for Photonic Network-on-Chips”, Journal of Lightwave Technology, vol. 30, 2012, pp. 368-376.10.1109/JLT.2011.2178019
  11. [11] K. Preston, N. Sherwood-Droz, J. S. Levy, and M. Lipson, “Per- formance Guidelines for WDM Interconnects based on Silicon Microring Resonators”, CLEO: Science and Innovations, 2011, p. CThP4.10.1364/CLEO_SI.2011.CThP4
  12. [12] C. Batten, A. Joshi, J. Orcutt, A. Khilo, B. Moss, C. Holzwarth et al , “Building Manycore Processor-to-Dram Networks with Monolithic Silicon Photonics”, High Performance Interconnects, 2008. HOTI’08. 16th IEEE Symposium on, 2008, pp. 21-30.10.1109/HOTI.2008.11
  13. [13] K. Chen, H. Gu, Y. Yang and D. Fan, “A Novel Two-Layer Passive Optical Interconnection Network for On-Chip Com- munication”, Journal of Lightwave Technology, vol. 32, 2014, pp. 1770-1776.10.1109/JLT.2014.2311119
  14. [14] N. Kirman and J. F. Mart´ınez, “A Power-Efficient All-Optical On-Chip Interconnect Using Wavelength-Based Oblivious Rout- ing”, ACM Sigplan Notices, 2010, pp. 15-28.10.1145/1735971.1736024
  15. [15] A. Shacham, K. Bergman and L. P. Carloni, “Photonic Net- works-On-Chip for Future Generations of Chip Multiproces- sors”, IEEE Transactions on Computers, vol. 57, 2008, pp. 1246-1260.10.1109/TC.2008.78
  16. [16] Z. Chen, H. Gu, Y. Yang and K. Chen, “Low Latency and Energy Efficient Optical Network-On-Chip using Wavelength Assignment”, IEEE Photonics Technology Letters, vol. 24, 2012, pp. 2296-2299.10.1109/LPT.2012.2226939
  17. [17] Z. Chen, H. Gu, Y. Yang and D. Fan, “A Hierarchical Optical Network-On-Chip Using Central-Controlled Subnet and Wave- length Assignment”, Journal of Lightwave Technology, vol. 32, 2014, pp. 930-938.10.1109/JLT.2013.2294863
  18. [18] P. Koonath and B. Jalali, “Multilayer 3-D Photonics Silicon”, Optics Express, vol. 15, 2007, pp. 12686-12691.10.1364/OE.15.012686
  19. [19] A. Biberman, N. Sherwood-Droz, X. Zhu, K. Preston, G. Hendry, S. Levy et al , “Photonic Network-On-Chip Architec- ture Using 3D Integration”, SPIE OPTO, 2011, pp. 79420M-79420M-4.10.1117/12.880152
  20. [20] A. Biberman, K. Preston, G. Hendry, N. Sherwood-Droz, J. Chan, S., Levy et al , “Photonic Network-On-Chip Architectures Using Multilayer Deposited Silicon Materials for High-Performance Chip Multiprocessors”, ACM Journal on Emerging Tech- nologies Computing Systems (JETC), vol. 7, 2011, p. 7.10.1145/1970406.1970409
  21. [21] X. Zhang and A. Louri, “A Multilayer Nanophotonic Inter- connection Network for On-Chip Many-Core Communications”, Proceedings of the 47th Design Automation Conference, 2010, pp. 156-161.10.1145/1837274.1837314
  22. [22] R. W. Morris, A. K. Kodi, A. Louri and R. D. Whaley, “Three-Dimensional Stacked Nanophotonic Network-On-Chip Architecture with Minimal Reconfiguration”, IEEE Transac- tions on Computers, vol. 63, 2014, pp. 243-255.10.1109/TC.2012.183
  23. [23] P. Carloni. P. Pande and Y. Xie, “Networks-On-Chip Emerging Interconnect Paradigms: Advantages and Challenges”, Proceed- ings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, 2009, pp. 93-102.10.1109/NOCS.2009.5071456
  24. [24] L. Ramini, P. Grani, D. S. Bartolini and D. Bertozzi, “Con- trasting Wavelength-Routed Optical NoC Topologies for Power- Efficient 3D-Stacked Multicore Processors using Physical-Layer Analysis”, Proceedings of the Conference on Design, Automa- tion and Test Europe, 2013, pp. 1589-1594.10.7873/DATE.2013.323
  25. [25] J. T. Bessette and D. Ahn, ”Vertically Stacked MicroringWaveg- uides for Coupling between Multiple Photonic Planes”, Optics Express, vol. 21, 2013, pp. 13580-13591.10.1364/OE.21.01358023736611
  26. [26] R. Morris, A. K. Kodi and A. Louri, “3D-NoC: Reconfigurable 3D Photonic On-Chip Interconnect for Multicores”, IEEE 30th Int. Conf. Computer Design (ICCD), pp. 413-418, 2012.10.1109/ICCD.2012.6378672
  27. [27] D. G. Rabus, Integrated Ring Resonators, Springer, 2007.
  28. [28] F. Xia, L. Sekaric and Y. Vlasov, “Ultracompact Optical Buffers on a Silicon Chip”, Nature photonics, vol. 1, 2007, pp. 65-71.10.1038/nphoton.2006.42
  29. [29] Y. Vlasov, W. M. Green and F. Xia, “High-Throughput Sili- con Nanophotonic Wavelength-Insensitive Switch for On-Chip Optical Networks”, Nature photonics, vol. 2, 2008, pp. 242-246.10.1038/nphoton.2008.31
  30. [30] B. G. Lee, A. Biberman, N. Sherwood-Droz, C. B. Poitras, M. Lipson and K. Bergman, “High-Speed 2 × 2 Switch for Mul- tiwavelength Silicon-Photonic Networks-On-Chip”, Journal of Lightwave Technology, vol. 27, 2009, pp. 2900-2907.10.1109/JLT.2009.2019256
DOI: https://doi.org/10.2478/jee-2018-0030 | Journal eISSN: 1339-309X | Journal ISSN: 1335-3632
Language: English
Page range: 226 - 232
Submitted on: Jan 22, 2018
|
Published on: Jul 28, 2018
In partnership with: Paradigm Publishing Services
Publication frequency: 6 issues per year

© 2018 Mohammad Reza Mokhtari, Hamed Baghban, Hadi Soofi, published by Slovak University of Technology in Bratislava
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.