Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Aytar, Oktay

doi:10.2478/jee-2015-0041

Abstract

This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (−0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

References

[1] MAUNTRICHAS, L.-SISKOS, S. : A High-Speed Offset Cancelling Distributed Sample-and-Hold Architecture for Flash A/D Converters, Microelectronics Journal 44 (2013), 1123-1131.10.1016/j.mejo.2013.06.016
Search in Google Scholar
[2] LIN, Y. Z.-LIN, C. W.-CHANG, S. J. : A 5-Bit 3.2-GS/s Flash ADC with a Digital Offset Calibration Scheme, IEEE Transactions on Very Large Scale Integration(VLSI) Systems 18 No. 3 (March 2010), 509-513.10.1109/TVLSI.2009.2013628
Search in Google Scholar
[3] MIN, Y. J.-ABDULLAH, A.-KIM, H. K.-KIM, S. W. : A 5-Bit 500-MS/s Time-Domain Flash ADC in 0.18 μm CMOS, 13th International Symposium on Integrated Circuits(ISIC), 2011, pp. 336-339.10.1109/ISICir.2011.6131965
Search in Google Scholar
[4] TAGHIZADEH, M. J.-SANUSI, M.-MOHD. ALI, M. A. : A 4.1-Bit, 20 GS/s Comparator for High Speed Flash ADC in 45 nm CMOS Technology, Journal of Microelectronics, Electronic Components and Materials 42 No. 1 (2012), 73-76.
Search in Google Scholar
[5] MATSUNA, J.-HOSOYA, M.-FURUTA, M.-ITAKURA, T. : A 3-GS/s 5-Bit Flash ADC with Wideband Input Buffer Amplifier, International Symposium on VLSI Design, Automation, and Test(VLSI-DAT), 2013, pp. 1-4.10.1109/VLDI-DAT.2013.6533840
Search in Google Scholar
[6] MOLOBERTI, F. : Data Converters, Springer, The Netherlands, 2007.
Search in Google Scholar
[7] HUANG, X.-LI, L.-ZHANG, Z.-CHEN, L.-YU, J. : High- Speed Comparator used for High-Speed, High-Resolution A/D Converter, International Conference on Anti-Counterfeiting Security and Identification in Communication (ASID), 2010, pp. 67-70.10.1109/ICASID.2010.5551835
Search in Google Scholar
[8] LIN, J.-MANO, I.-MIYAHARA, M.-MATSUZAWA, A. : Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product, IEEE Transactions on Very Large Scale Integration(VLSI) Systems, Accepted, (2015).
Search in Google Scholar
[9] DANJO, T.-YOSHIOKA, M.-ISOGAI, M.-HOSHINO, M. -TSUKAMOTO, S. : A 6-Bit, 1-GS/s, 9.9 mW, Interpolated Subranging ADC in 65 nm CMOS, IEEE Journal of Solid-State Circuits 49 No. 3 (2014), 673-682.10.1109/JSSC.2013.2297416
Search in Google Scholar
[10] HUANG, G.-LIN, P. : A 1.0 V 6-b 40MS/s time-domain flash ADC in 0.18 μm CMOS, Analog Integrated Circuits and Signal Processing 77 No. 2 (2013), 285-289.10.1007/s10470-013-0167-y
Search in Google Scholar
[11] DAE, S.-YOON, K. S. : Design of a 6-bit 500 MS/s CMOS A/D converter with Comparator-based Input Voltage Range Detection Circuit, Journal of Semiconductor Technology and Science 14 No. 6 (2014), 706-711.10.5573/JSTS.2014.14.6.706
Search in Google Scholar
[12] BABAYAN-MASHHADI, S.-LOTFI, R. : Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator, IEEE Transactions on Very Large Scale Integration(VLSI) Systems 22 No. 2 (2014), 343-352.10.1109/TVLSI.2013.2241799
Search in Google Scholar
[13] RAZAVI, B.-WOOLEY, B. A. : Design Techniques for High- Speed, High Resolution Comparators, IEEE Journal of Solid- State Circuits 27 No. 12 (1992), 1916-1926.10.1109/4.173122
Search in Google Scholar
[14] GAO, Y.-WANG, Y.-LI, R.-CHEN, G.-ZHANG, Z.- SHU, C.-ZHANG, L.-YE, R.-HU, R. : Dynamic Latched Comparator Design for Super-High Speed Analog-to-Digital Converter, International Conference on Anti-Counterfeiting Security and Identification in Communication (ASID), 2013, pp. 1-4.10.1109/ICASID.2013.6825297
Search in Google Scholar
[15] TANGEL, A.-CHOI, K. : The CMOS Inverter as a Comparator in ADC Designs, Analog Integrated Circuits and Signal Processing 39 (2004), 147-155.10.1023/B:ALOG.0000024062.35941.23
Search in Google Scholar
[16] MARQUEZ, F.-MUNOZ, F.-CARVAJAL, R. G.-GARCIAOYA, J. R.-LOPEZ-MORILLA, E.-TORRALBA, A.-GALAN, J. : A Novel Autozeoring Technique for Flash Analog- to-Digital Converters, Integration, the VLSI Journal 47 (2014), 23-29.10.1016/j.vlsi.2013.06.002
Search in Google Scholar
[17] CHEN, M.-LU, W.-TAO, T.-ZHANG, Y.-CHEN, Z. : A Low-Power Auto-Zeroed Comparator for Column-Paralleled 14 SAR ADCs of 384x288 IRFPA ROIC, International Conference on Electron Devices and Solid-State Circuits(EDSSC), 2013, pp. 1-2.
Search in Google Scholar
[18] LEE, C. C.-YANG, C. M.-KUO, T. H. : A Compact Low- Power ADC using Auto-Zeroing with Capacitor Averaging, International Conference on Electron Devices and Solid-State Circuits( EDSSC), 2013, pp. 1-2.
Search in Google Scholar
[19] HUANG, Y.-SCHLEIFER, H.-KILLAT, D. : Design and Analysis of Novel Dynamic Latched Comparator with Reduced Kickback Noise for High-Speed ADCs, European Conference on Circuit Theory and Design(ECCTD), 2013, pp. 1-4.10.1109/ECCTD.2013.6662236
Search in Google Scholar
[20] ALLEN, P. E.-HOLBERG, D. R. : CMOS Analog Circuit Design, Oxford University Press, second edition, New York, 2002.
Search in Google Scholar
[21] SAIL, E.-VESTERBACKA. : A Multiplexer Decoder for Flash Analog-to-Digital Converters, IEEE Region 10 Conference TENCON, Fukuoka, Japan, 2004, pp. 250-253.
Search in Google Scholar
[22] http://inst.eecs.berkeley.edu/˜n247/matlab files/inldnl.m, (Visiting date 22nd April 2015).
Search in Google Scholar
[23] VARZAGHANI, A.-YANG, C. K. K. : A 4.8GS/s 5-Bit ADC-Based Receiver with Embedded DFE for Signal Equalization, IEEE Journal of Solid-State Circuits 44 No. 3 (2009), 901-915.10.1109/JSSC.2009.2013765
Search in Google Scholar
[24] SHIWEN, L.-HUA, D.-PENG, G.-XIAOYAN, G.-ZHIMING, C.-XINGHUA, W.-SHUNAN, Z. : Design and Implementation of a CMOS 1 Gsps 5 bit Flash ADC with Offset Calibration, IEEE International Conference on Green Computing and Communications (GreenCom) and IEEE Internet of Things (iThings/CPSCom), and IEEE Cyber, Physical and Social Computing, 2013, pp. 1829-1833.10.1109/GreenCom-iThings-CPSCom.2013.339
Search in Google Scholar
[25] LIN, Y. Z.-CHANG, S. J-LIU, Y. T. : A 5-Bit 4.2 GS/s Flash ADC in 0.13 μm CMOS Process, IEICE Transactions on Electronics E92-C No. 2 (2009), 258-268. 10.1587/transele.E92.C.258
Search in Google Scholar

Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

Abstract

Paradigm

My account