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A Multi–Alphabet Arithmetic Coding Hardware Implementation for Small FPGA Devices Cover

A Multi–Alphabet Arithmetic Coding Hardware Implementation for Small FPGA Devices

Journal of Electrical Engineering
Volume 64 (2013): Issue 1 (January 2013)
By: Anton Biasizzo,  Franc Novak and  Peter Korošec  
Open Access
|Mar 2013

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DOI: https://doi.org/10.2478/jee-2013-0006 | Journal eISSN: 1339-309X | Journal ISSN: 1335-3632
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Language: English
Page range: 44 - 49
Published on: Mar 9, 2013
Published by: Slovak University of Technology in Bratislava
In partnership with: Paradigm Publishing Services
Publication frequency: 6 issues per year
Keywords:
arithmetic coding,
compression algorithm
Related subjects:
Engineering,
Introductions and overviews,
Engineering, other

© 2013 Anton Biasizzo, Franc Novak, Peter Korošec, published by Slovak University of Technology in Bratislava
This work is licensed under the Creative Commons License.

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