Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets

Maciej Kopczyński; Tomasz Grześ

doi:10.2478/jaiscr-2021-0007

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Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets

Journal of Artificial Intelligence and Soft Computing Research

Volume 11 (2021): Issue 2 (April 2021)

By: Maciej Kopczyński and Tomasz Grześ

Open Access

|Jan 2021

Abstract

This paper presents FPGA and softcore CPU based solution for large datasets parallel core calculation using rough set methods. Architectures shown in this paper have been tested on two real datasets running presented solutions inside FPGA unit. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.

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Articles in this issue

DOI: https://doi.org/10.2478/jaiscr-2021-0007

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Language: English

Page range: 99 - 110

Submitted on: May 5, 2020

Accepted on: Nov 5, 2020

Published on: Jan 29, 2021

Published by: SAN University

In partnership with: Paradigm Publishing Services

Publication frequency: 4 issues per year

Keywords:

rough sets,

FPGA,

core attributes,

parallel architecture

Related subjects:

Computer sciences,

Artificial intelligence,

Databases and data mining

© 2021 Maciej Kopczyński, Tomasz Grześ, published by SAN University
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Volume 11 (2021): Issue 2 (April 2021)