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Design and Implementation of Low Power and High Data Rate Edge Coded Signaling Architecture for IoT Devices Cover

Design and Implementation of Low Power and High Data Rate Edge Coded Signaling Architecture for IoT Devices

International Journal on Smart Sensing and Intelligent Systems
Volume 17 (2024): Issue 1 (January 2024)
By:  and    
Open Access
|Sep 2024
Figures & tables

Figures & Tables

Figure 1:

Architecture of a CDR circuit using PLL. CDR, clock and data recovery; PLL, phase-locked loop.

Table 1:

Comparison of IoT communication protocols

Wired protocolsWireless protocol
Characteristics1-wire protocolPIC protocolPDC protocolDynamic ECS protocolBluetooth graphic/j_ijssis-2024-0029_ingr_001.pnggraphic/j_ijssis-2024-0029_ingr_002.png ZigbeeZ-wave graphic/j_ijssis-2024-0029_ingr_003.png6 LoWPAN graphic/j_ijssis-2024-0029_ingr_004.pngSigFox graphic/j_ijssis-2024-0029_ingr_005.png
StandardNANANANAIEEE 802.15.1 [20]IEEE 802.15.4 [20]Z-Wave [20]IEEE 802.15.4 [20]Sigfox [21]
Frequency bandsNA24 MHz [16]25 MHz [17]25 MHz [18]2.4 GHz [22]2.4 GHz [23]868–908 MHz [24]868 MHz (EU)868 MHz (EU)
915 MHz (USA)902 MHz (USA)
2.4 GHz (Global) [24]
Network1-wire network [8]Ultra-low power network [16]Ultra-low power network [17]Ultra-low power network [18]WPAN [25]WPAN [25]WPAN [25]WPAN [25]LPWAN [26]
TopologyMaster and Slave [8]Master and Slave [16]Master and Slave [17]Master and Slave [18]Star–Bus [27]Star, Mesh clusterMeshStar-Mesh [27]Star
PowerLow power protocol26.6 μW [16]25 μW [17]19 μW [18]30 mA Low power [28]30 mA Low power [28]2.5 mA Low power [29](1–2 years lifetime on batteries) [29]10–100 mW
Data rate16 Kbps [16]4.1 Mbps [16]7.33 Mbps [17]4.2–26.7 (6.4 Avg.) [18]1 Mbps250 Kbps40 Kbps [30]250 Kbps100–600 bps
Common applicationsIoT sensor applications [16]IoT sensor applications [16]IoT sensor applications [17]IoT sensor applications [18]Wireless headsets, audio applications [31]Controlling and monitoring home industry [31]Home monitoring and controlling [31]Monitor and control through the internet [31]Energy meters & street lighting

[i] ECS, edge coded signaling; IoT, internet of things; PDC, pulsed decimal communication; PIC, pulsed index communication.

Figure 2:

(A) Normal serial transfer; (B) Edge-coded transmitter; (C) Edge-coded.

Figure 3:

ECS packet formation. ECS, edge coded signaling.

Figure 4:

Example: ECS packet formation. ECS, edge coded signaling.

Figure 5:

Standard ECS transmission (Data = 267). ECS, edge coded signaling.

Figure 6:

(A) Standard ECS transmission (Data = 267) (B) DDR-ECS transmission = (Data = 267) (C) DDR-ECS transmission (Data = 132). DDR, double data rate; ECS, edge coded signaling.

Figure 7:

Proposed DDR-ECS architecture. DDR, double data rate; ECS, edge coded signaling.

Figure 8:

Segmentation/bit splitter.

Figure 9:

Simulation result showing data segmentation for input 3EC8.

Table 2:

Encoded data and number of 1’s

Regular dataEncoding/inversionNumber of 1’sFlag
0000000000
0001000110
0010001010
0011001120
0100010010
0101010120
0110011020
0111100011
1000100010
1001100120
1010101020
1011010011
1100110020
1101001011
1110000111
1111000001
Figure 10:

Segment encoder.

Figure 11:

Simulation results showing Index codes and NOIs.

Figure 12:

Index code generation.

Table 3:

Index coding

Possible data after encodingNo. of pulses (existing) [8, 9]Number of 1’sIndex codeNo. of pulses (proposed)
0001110011
0010210102
0100310113
1000411004
0011320011
0101420102
0110520113
1001521004
1010621015
1100721106
Figure 13:

Simulation result showing encoded data.

Figure 14:

Simulation result showing Index one output.

Figure 15:

Simulation result showing Index two output.

Figure 16:

Simulation result showing Flag bit.

Figure 17:

Proposed DDR-ECS packet. DDR, double data rate; ECS, edge coded signaling.

Figure 18:

FSM implementation of proposed DDR-ECS transmitter. DDR, double data rate; ECS, edge coded signaling.

Figure 19:

Simulation result showing subsequent iterations.

Figure 20:

Toggle counter.

Figure 21:

Example of DDR-ECS pulse generation using toggle counter. DDR, double data rate; ECS, edge coded signaling.

Figure 22:

Simulation result showing generation of transmission pulse for the input 3EC8.

Figure 23:

Positive edge detector.

Figure 24:

Positive edge detection.

Figure 25:

Negative edge detector.

Figure 26:

Negative edge detection.

Figure 27:

Counter enable generation.

Figure 28:

Rising and falling edge of a pulse.

Figure 29:

Simulation result of counter 1.

Figure 30:

Simulation result of counter 2.

Figure 31:

Simulation result of memory unit.

Figure 32:

Simulation result of data decoder.

Figure 33:

Simulation output of 16-bit DDR ECS transmitter module with data input 4539.Double data rate ECS.

Figure 34:

Simulation output of 16-bit DDR ECS receiver module with data input 4539. Double data rate ECS.

Table 4:

DDR-ECS transceiver synthesis results using 65 nm technology

Name of the modulePower (µW)Area (µm2)Data rate (Mb/s)
Proposed 16 bit DDR-ECS≈131,75512–73.5
DDR-ECS [10]≈191,9437.8–44.4
ECS [9]≈19≈2,0984.2–26.7
PDC [4]≈25≈2,1504.8–12.9
PIC [3]≈26.6≈2,3563.1–8.5

[i] DDR, double data rate; ECS, edge coded signaling; PDC, pulsed decimal communication; PIC, pulsed index communication.

DOI: https://doi.org/10.2478/ijssis-2024-0029 | Journal eISSN: 1178-5608
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Language: English
Submitted on: May 19, 2024
Published on: Sep 28, 2024
Published by: International Journal on Smart Sensing and Intelligent Systems
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
Edge coded signaling (ECS),
Double data rate ECS,
IoT,
Low power
Related subjects:
Engineering,
Introductions and overviews,
Engineering, other

© 2024 M Jamuna, A. M VijayaPrakash, published by International Journal on Smart Sensing and Intelligent Systems
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Volume 17 (2024): Issue 1 (January 2024)
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