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Towards a design space exploration methodology for system-on-chip Cover

Towards a design space exploration methodology for system-on-chip

Cybernetics and Information Technologies
Volume 14 (2014): Issue 1 (March 2014)
By: A. Chariete,  M. Bakhouya,  J. Gaber and  M. Wack  
Open Access
|Apr 2014
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DOI: https://doi.org/10.2478/cait-2014-0008 | Journal eISSN: 1314-4081 | Journal ISSN: 1311-9702
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Language: English
Page range: 101 - 111
Published on: Apr 9, 2014
Published by: Bulgarian Academy of Sciences, Institute of Information and Communication Technologies
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year
Keywords:
System-on-Chip,
On-chip interconnect,
simulation,
performance evaluation,
design-space exploration
Related subjects:
Computer sciences,
Information technology

© 2014 A. Chariete, M. Bakhouya, J. Gaber, M. Wack, published by Bulgarian Academy of Sciences, Institute of Information and Communication Technologies
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.

Volume 14 (2014): Issue 1 (March 2014)
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