A New Model of Dynamic Logic Circuit with NMOS based Keeper

Riazul Islam; Satyendra N. Biswas

doi:10.2478/auseme-2020-0001

Abstract

Dynamic logic circuits are widely popular due to a smaller number of transistors and consume less area. But the time to switch between logics is higher due to higher contention value. A new model of the logic using nMOS based keeper circuit is proposed and the performance is evaluated using Cadence tools. Comparative results demonstrate the suitability and competency of the proposed circuit.

References

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A New Model of Dynamic Logic Circuit with NMOS based Keeper

Abstract

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