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Cost factor analysis for the FPGA design of 128-bit SSC Cryptoprocessor_
| Design area analysis | The number of logic elements (LEs) | 58,719 LEs |
|---|---|---|
| The number of four-input look-up table | 234,876 LUTs | |
| The number of registers | 29,883 | |
| Memory utilization | 50% | |
| Total number of I/O pins | 389 | |
| I/O utilization | 76% | |
| Design timing analysis | Total path delay for critical clock cycle | 25.02 ns |
| Maximum frequency | 40 MHz | |
| Critical clock cycles to perform SSC process | 5 million clocks | |
| Total processing delay to perform SSC process | 125 ms | |
| Design power analysis | Dynamic thermal power dissipation (I/O assignments and operations) | 102.6 mW |
| Static thermal power dissipation | 148.7 mW | |
| Total FPGA thermal power dissipation | 251.3 mW |