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Implementation of 144 × 64 Pixel Array Bezel-Less Cmos Fingerprint Sensor

International Journal on Smart Sensing and Intelligent Systems
Volume 11 (2018): Issue 1 (January 2018)
By:
Open Access
|Sep 2018

Figures & Tables

Fig. 1

Pixel-level sensor scheme and output voltage.
Pixel-level sensor scheme and output voltage.

Fig. 2

Functional block diagram of fingerprint sensor chip.
Functional block diagram of fingerprint sensor chip.

Fig. 3

Pipelined scan fingerprint sensor driver architecture.
Pipelined scan fingerprint sensor driver architecture.

Fig. 4

Floorplan of fingerprint sensor chip.
Floorplan of fingerprint sensor chip.

Fig. 5

RTL simulation result of pipelined architecture.
RTL simulation result of pipelined architecture.

Fig. 6

144 × 64 pixel array chip layout (7,569 μm × 4,569 μm @0.35 μm CMOS process)
144 × 64 pixel array chip layout (7,569 μm × 4,569 μm @0.35 μm CMOS process)
DOI: https://doi.org/10.21307/ijssis-2018-013 | Journal eISSN: 1178-5608
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Language: English
Page range: 1 - 5
Published on: Sep 3, 2018
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 times per year
Keywords:
Bezel-less,
capacitive fingerprint,
fingerprint sensor,
readout circuit,
switched capacitive integrator
Related subjects:
Engineering,
Introductions and overviews,
Engineering, other

© 2018 Seungmin Jung, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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