Fig. 1
Pixel-level sensor scheme and output voltage.
Fig. 2
Functional block diagram of fingerprint sensor chip.
Fig. 3
Pipelined scan fingerprint sensor driver architecture.
Fig. 4
Floorplan of fingerprint sensor chip.
Fig. 5
RTL simulation result of pipelined architecture.
Fig. 6
144 × 64 pixel array chip layout (7,569 μm × 4,569 μm @0.35 μm CMOS process)