Authors
P. Saha
Bengal Engineering and Science University, Shibpur, India
A. Banerjee
Dept. of ECE, JIS College of Engineering, Kalyani, India
A. Dandapat
Department of ETCE. Jadavpur University, India
Vedic Mathematics Based 32-Bit Multiplier Design for High Speed Low Power Processors
By: P. Saha, A. Banerjee, A. Dandapat and P. Bhattacharyya
DOI: https://doi.org/10.21307/ijssis-2017-439 | Journal eISSN: 1178-5608
Language: English
Page range: 268 - 284
Submitted on: May 9, 2011
|Accepted on: May 25, 2011
|Published on: Jun 1, 2011
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
Related subjects:
© 2011 P. Saha, A. Banerjee, A. Dandapat, P. Bhattacharyya, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.