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Performance and Analysis of Low Power, Areaefficient and High Speed Carryfast Adder Cover

Performance and Analysis of Low Power, Areaefficient and High Speed Carryfast Adder

International Journal on Smart Sensing and Intelligent Systems
Volume 10 (2017): Issue 5 (January 2017)
By: M. AntoBennet,  S. Sankaranarayanan,  V. BanuPriya,  PJaya Pretheena,  S. Yamini and  S. Supriya  
Open Access
|Sep 2017

Authors

M. AntoBennet

bennetmab@gmail.com

Faculty of Electronics and Communication Department, vel tech, Chennai, India

S. Sankaranarayanan

UG Students of Electronics and Communication Department, vel tech, Chennai, India

V. BanuPriya

UG Students of Electronics and Communication Department, vel tech, Chennai, India

PJaya Pretheena

UG Students of Electronics and Communication Department, vel tech, Chennai, India

S. Yamini

UG Students of Electronics and Communication Department, vel tech, Chennai, India

S. Supriya

UG Students of Electronics and Communication Department, vel tech, Chennai, India
DOI: https://doi.org/10.21307/ijssis-2017-268 | Journal eISSN: 1178-5608
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Language: English
Page range: 522 - 538
Submitted on: May 27, 2017
Accepted on: Jun 15, 2017
Published on: Sep 1, 2017
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
Carry Select Adder (CSLA),
Binary to Excess-1 Converter (BEC),
Carry-propagation adder (CPA)
Related subjects:
Engineering,
Introductions and overviews,
Engineering, other

© 2017 M. AntoBennet, S. Sankaranarayanan, V. BanuPriya, PJaya Pretheena, S. Yamini, S. Supriya, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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