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Computation of Field Programmable Cyclic Redundancy Checks Circuit Architecture Cover

Computation of Field Programmable Cyclic Redundancy Checks Circuit Architecture

International Journal on Smart Sensing and Intelligent Systems
Volume 10 (2017): Issue 5 (January 2017)
By: M. Anto Bennet,  Lakshmi Ravali,  T.R. Sughapriya,  J. Jenitta,  K. Vaishnavi and  Priyanka Paree Alphonse  
Open Access
|Sep 2017

Authors

M. Anto Bennet

bennetmab@gmail.com

Faculty of Electronics and Communication Department, Vel tech, Chennai, India

Lakshmi Ravali

UG Students of Electronics and Communication Department, Vel tech, Chennai, India

T.R. Sughapriya

UG Students of Electronics and Communication Department, Vel tech, Chennai, India

J. Jenitta

UG Students of Electronics and Communication Department, Vel tech, Chennai, India

K. Vaishnavi

UG Students of Electronics and Communication Department, Vel tech, Chennai, India

Priyanka Paree Alphonse

UG Students of Electronics and Communication Department, Vel tech, Chennai, India
DOI: https://doi.org/10.21307/ijssis-2017-267 | Journal eISSN: 1178-5608
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Language: English
Page range: 506 - 521
Submitted on: May 27, 2017
Accepted on: Jun 15, 2017
Published on: Sep 1, 2017
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
Cyclic Redundancy Check (CRC),
Application Specific Integrated Circuit,
ASIC
Related subjects:
Engineering,
Introductions and overviews,
Engineering, other

© 2017 M. Anto Bennet, Lakshmi Ravali, T.R. Sughapriya, J. Jenitta, K. Vaishnavi, Priyanka Paree Alphonse, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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