Computation of Field Programmable Cyclic Redundancy Checks Circuit Architecture
Authors
M. Anto Bennet
Faculty of Electronics and Communication Department, Vel tech, Chennai, India
Lakshmi Ravali
UG Students of Electronics and Communication Department, Vel tech, Chennai, India
T.R. Sughapriya
UG Students of Electronics and Communication Department, Vel tech, Chennai, India
J. Jenitta
UG Students of Electronics and Communication Department, Vel tech, Chennai, India
K. Vaishnavi
UG Students of Electronics and Communication Department, Vel tech, Chennai, India
Priyanka Paree Alphonse
UG Students of Electronics and Communication Department, Vel tech, Chennai, India
DOI: https://doi.org/10.21307/ijssis-2017-267 | Journal eISSN: 1178-5608
Language: English
Page range: 506 - 521
Submitted on: May 27, 2017
Accepted on: Jun 15, 2017
Published on: Sep 1, 2017
Published by: Macquarie University, Australia
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Related subjects:
© 2017 M. Anto Bennet, Lakshmi Ravali, T.R. Sughapriya, J. Jenitta, K. Vaishnavi, Priyanka Paree Alphonse, published by Macquarie University, Australia
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.