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Design of Low Leakage Current Average Power CMOS Current Comparator Using SVL Technique With Pseudo NMOS and Transmission Gate Logics Cover

Design of Low Leakage Current Average Power CMOS Current Comparator Using SVL Technique With Pseudo NMOS and Transmission Gate Logics

International Journal on Smart Sensing and Intelligent Systems
Volume 10 (2017): Issue 5 (January 2017)
By: T.R. Dinesh Kumar,  K. Mohana Sundaram,  M. Anto Bennet,  M. Pooja,  A.P. Kokila and  K. Anusuya  
Open Access
|Sep 2017

Authors

T.R. Dinesh Kumar

Faculty of Electronics and Communication Engineering,Vel Tech, Chennai, India

K. Mohana Sundaram

Faculty of Electronics and Communication Engineering,Vel Tech, Chennai, India
Faculty of Electrical and Electronics Engineering,Vel Tech Multitech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, India

M. Anto Bennet

bennetmab@gmail.com

Faculty of Electronics and Communication Engineering,Vel Tech, Chennai, India

M. Pooja

UG Student of Electronics and Communication Engineering,Vel Tech, Chennai, India

A.P. Kokila

UG Student of Electronics and Communication Engineering,Vel Tech, Chennai, India

K. Anusuya

UG Student of Electronics and Communication Engineering,Vel Tech, Chennai, India
DOI: https://doi.org/10.21307/ijssis-2017-256 | Journal eISSN: 1178-5608
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Language: English
Page range: 344 - 357
Submitted on: May 27, 2017
Accepted on: Jun 15, 2017
Published on: Sep 1, 2017
Published by: Professor Subhas Chandra Mukhopadhyay
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
current comparator,
SVL circuit,
pseudo nmos,
transmission gate,
low power consumption,
standby mode
Related subjects:
Engineering,
Introductions and overviews,
Engineering, other

© 2017 T.R. Dinesh Kumar, K. Mohana Sundaram, M. Anto Bennet, M. Pooja, A.P. Kokila, K. Anusuya, published by Professor Subhas Chandra Mukhopadhyay
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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