Design of Low Leakage Current Average Power CMOS Current Comparator Using SVL Technique With Pseudo NMOS and Transmission Gate Logics
Authors
T.R. Dinesh Kumar
Faculty of Electronics and Communication Engineering,Vel Tech, Chennai, India
K. Mohana Sundaram
Faculty of Electronics and Communication Engineering,Vel Tech, Chennai, India
Faculty of Electrical and Electronics Engineering,Vel Tech Multitech Dr. Rangarajan Dr. Sakunthala Engineering College, Chennai, India
M. Anto Bennet
Faculty of Electronics and Communication Engineering,Vel Tech, Chennai, India
M. Pooja
UG Student of Electronics and Communication Engineering,Vel Tech, Chennai, India
A.P. Kokila
UG Student of Electronics and Communication Engineering,Vel Tech, Chennai, India
K. Anusuya
UG Student of Electronics and Communication Engineering,Vel Tech, Chennai, India
DOI: https://doi.org/10.21307/ijssis-2017-256 | Journal eISSN: 1178-5608
Language: English
Page range: 344 - 357
Submitted on: May 27, 2017
Accepted on: Jun 15, 2017
Published on: Sep 1, 2017
Published by: Macquarie University, Australia
In partnership with: Paradigm Publishing Services
Publication frequency: 1 issue per year
Keywords:
Related subjects:
© 2017 T.R. Dinesh Kumar, K. Mohana Sundaram, M. Anto Bennet, M. Pooja, A.P. Kokila, K. Anusuya, published by Macquarie University, Australia
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.