EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS

S. D. Thabah; M. Sonowal; P. Saha

doi:10.21307/ijssis-2017-214

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EXPERIMENTAL STUDIES ON MULTI-OPERAND ADDERS

International Journal on Smart Sensing and Intelligent Systems

Volume 10 (2017): Issue 2 (January 2017)

By: S. D. Thabah, M. Sonowal and P. Saha

Open Access

|Jun 2017

Abstract

In this paper, different multi-operand adders have been analyzed in terms of propagation delay, power consumption and resource utilization. The functionality of the adders have been verified using Verilog hardware description language and synthesized in Xilinx ISE. The device chosen for implementation is Virtex 6 (XC6VLX240T) with FF1156 package. Simulation results show that Wallace tree adder is the fastest adder and consumes least amount of power. The Wallace tree adder also consumes the least amount of hardware resources as per the synthesis results.

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Articles in this issue

DOI: https://doi.org/10.21307/ijssis-2017-214 | Journal eISSN: 1178-5608

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Language: English

Page range: 1 - 14

Submitted on: Feb 15, 2017

Accepted on: Apr 15, 2017

Published on: Jun 1, 2017

Published by: Macquarie University, Australia

In partnership with: Paradigm Publishing Services

Publication frequency: 1 issue per year

Keywords:

Multi-operand adders,

Related subjects:

Introductions and overviews,

Engineering, other

© 2017 S. D. Thabah, M. Sonowal, P. Saha, published by Macquarie University, Australia
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

Volume 10 (2017): Issue 2 (January 2017)