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A Fault Detection Method for Combinational Circuits Cover

References

  1. [1] J. Srinivasan, S. V. Adve, P. Bose, and J. A. Rivers, “The impact of technology scaling on lifetime reliability,” presented at the INT. Conf. Dependable Systems and Networks, June 2004.10.1109/DSN.2004.1311888
  2. [2] K. Mohanram, and N. A. Touba, “Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits,” presented at the ITC. Conf. International Test Conference, 2003, pp. 893.
  3. [3] P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, “Modeling the effect of technology trends on the soft error rate of combinational logic,” presented at the DSN. Conf. Proceedings of International Conference on Dependable Systems and Networks, June 2002, p. 389–98.
  4. [4] S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and D. Vivek, “Parameter variations and impact on circuits and microarchitecture,” presented at the Conf. Design Automation, June 2003.10.1145/775832.775920
  5. [5] K. Constantinides, S. Plaza, J. Blome, B. Zhang, V. Bertacco, S. Mahlke, T. Austin, and M. Orshansky, “Bulletproof: A defect-tolerant CMP switch architecture,” presented at the INT. Conf. Symposium on High Performance Computer Architecture, February 2006.
  6. [6] V. Narayanan, and Y. Xie, “Reliability concerns in embedded system designs,” presented at the Conf. IEEE Computer Society, Jan 2006, 39(1):118–20.10.1109/MC.2006.31
  7. [7] D. T. Franco, J. F. Naviner, and L. Naviner, “Yield and reliability issues in nanoelectronic technologies,” presented at the ANN. Conf. Telecommunication, 2006, 61(11–12):1422–57.10.1007/BF03219903
  8. [8] J. F. Zielger, and H. Puchner, “SER-History, Trends and Challenges,” presented at the Conf. Cypress Semiconductor Corporation, 2004.
  9. [9] V. Stojanovic, “A Cost-Effective Implementation of an ECC-Protected Instruction Queue for Out-of-Order Microprocessors,” presented at the DAC. Conf., 2006.10.1145/1146909.1147087
  10. [10] S. Mukherajee, “Architectural Design for Soft Errors,” in Morgan Kaufmann Publishers, 2008.
  11. [11] B. Johnson, “Design and Analysis of Fault-Tolerant Digital Systems,” in Addison Wesley Reading MA, 1989.10.1007/978-3-642-75002-1_5
  12. [12] J. A. Blome, S. Gupta, S. Feng, and S. Mahlke, “Cost-efficient soft error protection for embedded microprocessors,” in CASES, 2006, pp. 421–31.10.1145/1176760.1176811
  13. [13] S. Mukherjee, J. Emer, and S. Reinhardt, “The Soft-Error Problem: An Architectural Perspective,” presented at the HPCA-11 Conf. 11th INT. Symp. High Performance Computer Architecture, 2005.
  14. [14] R. K. Dyeriyer, and D. J. Rossetti, “A Measurement-Bascd Model for Workload Dependence of CPU Errors,” presented at the IEEE Trans. Comp., vol. C-35, pp. 511-19, June 1986.10.1109/TC.1986.5009428
  15. [15] Z. A. Obaid, N. Sulaiman, and M. N. Hamidon, “Developed Method of FPGA-based Fuzzy Logic Controller Design with the Aid of Conventional PID Algorithm,” presented at the Australian Journal of Basic and Applied Sciences, 2009, 3(3):2724-40.
  16. [16] K. Perkuszewski, K. T. Pozniak, W. Jalmuna, W. Koprek, J. Szewinski, and R. S. Romaniuk, “FPGA based Multichannel Optical Concenrator SIMCON 4.0,” presented at the TESLA cavities LLRF Control System, Deutsche Elektronen-Synchrotron (DESY), Germany, 2007.10.1117/12.714533
  17. [17] T. Siriwan, and P. Nilagupta, “HPGAST: High Performance GA-based Sequential circuits Test generation on Beowulf PC-Cluster,” presented at the Conf. Pahonyothin Rd. Lardyao Jatujak Bangkok 10900 Thailand, 2002.
  18. [18] F. Kocan, and D. G. Saab, “Dynamic Fault Diagnosis of Combinational and Sequential Circuits on Reconfigurable Hardware,” presented at the Journal of Electron Test, Springer Science, September 2007, 23:405–20.10.1007/s10836-007-5009-3
  19. [19] M. P. Baze, and S. P. Buchner, “Attenuation of Single Event Induced Pulses in CMOS Combinational Logic,” presented at the IEEE Trans. on Nuclear Science, Vol. 44, No. 6, pp. 2217–22, December 1997.
  20. [20] P. Liden, P. Dahlgren, R. Johansson, and J. Karlsson, “On Latching Probability of Particle Induced Transient in Combinatorial Networks,” presented at the 24th Symposium on Fault-Tolerant Computing (FTCS), pp. 340–49, June 1994.
  21. [21] M. D. Chinn, “Survey Based Expectations and Uncovered Interest Rate Parity,” University of Wisconsin, Madison and NBER, October 2009.
  22. [22] A. Saberkari, A. Afzalikosha, and S. B. Shokouhi, “A new low voltage and low power CMOS one bit full-adder using GDI technique,”presented at the 14th Iranian Conference on Electrical Engineering (ICEE), Amirkabir University, Tehran, Iran, May 2006.
Language: English
Page range: 1 - 5
Published on: Apr 1, 2018
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year

© 2018 AliAbbass Zoraghchian, Moslem Didehban, Mohammad Reza Mehrabian, published by Xi’an Technological University
This work is licensed under the Creative Commons Attribution 4.0 License.