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Current mode pulse width modulation/pulse position modulation based on phase lock loop Cover

Current mode pulse width modulation/pulse position modulation based on phase lock loop

Open Access
|Jul 2017

Abstract

In this paper, the fully integrated CMOS current mode PLL with current input injects at the place of input or output of the loop filter without summing amplifier circuit. It functions as PPM and PWM circuit is present. In addition, its frequency response is an analysis which electronic tuning BPF and LPF are obtained. The proposed circuit has been designed with 0.18 μm CMOS technology. The simulation results of this circuit can be operated at 2.5 V supply voltage, at center frequency 100 MHz. The linear range of input current can be adjusted from 43 μA to 109 μA, and the corresponding duty cycle of pulse width output is from 93% to 16% and the normalized pulse position is from 0.93 to 0.16. The power dissipation of this circuit is 4.68 mW with the total chip area is 28 μm × 60 μm.

DOI: https://doi.org/10.1515/jee-2017-0026 | Journal eISSN: 1339-309X | Journal ISSN: 1335-3632
Language: English
Page range: 180 - 187
Submitted on: Mar 18, 2017
Published on: Jul 6, 2017
Published by: Slovak University of Technology in Bratislava
In partnership with: Paradigm Publishing Services
Publication frequency: 6 issues per year

© 2017 Pichet Wisartpong, Vorapong Silaphan, Sunee Kurutach, Paramote Wardkein, published by Slovak University of Technology in Bratislava
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.