Design of Gigahertz Tuning Range 5 GHz LC Digitally Controlled Oscillator in 0.18 μm CMOS
By:
References
- [1] STASZEWSKI, R. B.-HUNG, C.-BARTON, N.-LEE, M.-LEIPOLD, D. : A Digitally Controlled Oscillator in a 90 nm Digital CMOS Process for Mobile Phones, IEEE J. Solid-State Circuits 40 No. 11 (2005), 2203-2211.
- [2] LU, P.-SJÖLAND, H. : A 5 GHz 90 nm CMOS All Digital Phase-Locked Loop, Analog Integrated Circuits and Signal Processing 66 No. 1 (2010), 49-59.
- [3] HSU, C.-STRAAYER, M.-PERROTT, M. : A Low-Noise Wide-BW 3.6 GHz Digital Δ∑ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation, IEEE J. Solid-State Circuits 43 No. 12 (2008), 2776-2786.
- [4] TEMPORITI, E.-WELTIN-WU, C.-BALDI, D.-TONIETTO, R.-SVELTO, F. : A 3 GHz Fractional All-Digital PLL with a 1.8 MHz Bandwidth Implementing Spur Reduction Techniques, IEEE J. Solid-State Circuits 44 No. 3 (2009), 824-834.
- [5] LIU, Y.-CHEN, W.-CHOU, M.-TSAI, T.-LEE, Y.-YUAN, M. : A 0.1-3GHz Cell-Based Fractional-N All Digital Phase-Locked Loop using Δ∑ Noise-Shaped Phase Detector, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013.
- [6] PLETCHER, N.-RABAEY, J. : A 100 μW, 1.9 GHz Oscillator with Fully Digital Frequency Tuning, Proceedings of the 31st European Solid-State Circuits Conference, 2005, pp. 387-390.
- [7] PITTORINO, T.-CHEN, Y.-NEUBAUER, V.-MAYER, T.-MAURER, L. : A UMTS-Complaint Fully Digitally Controlled Oscillator with 100 Mhz Fine-Tuning Range in 0.13 μm CMOS, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, pp. 770-779.
- [8] ZHUANG, J.-DU, Q.-KWASNIEWSKI, T. : A 3.3 GHz LC-Based Digitally Controlled Oscillator with 5 kHz frequency resolution, 2007 IEEE Asian Solid-State Circuits Conference, 2007, pp. 428-431.
- [9] PU, Y.-PARK, A.-PARK, J. S.-LEE, K. Y. : Low-Power, All Digital Phase-Locked Loop with a Wide-Range, High Resolution TDC’, ETRI J, 33 No. 3 (2011), 366-373.
- [10] SAMARAH, A.-CARUSONE, A. : A Digital Phase-Locked Loop With Calibrated Coarse and Stochastic Fine TDC, IEEE J. Solid-State Circuits 48 No. 8 (2013), 1829-1841.
- [11] CHEN, X.-YANG, J.-SHI, L. : A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 19 No. 5 (2011), 857-868.
- [12] DENG, Z.-NIKNEJAD, A. M. : The Speed-Power Trade-Off in the Design of CMOS True-Single-Phase-Clock Divider, IEEE Journal of Solid-State Circuits 45 No. 11 (2010), 2457-2465.
- [13] JURGO, M.-KIELA, K.-NAVICKAS, R. : Design of Low Noise 10 GHz divide by 16 . . . 511 Frequency Divider, Electronics and Electrical Engineering 19 No. 6 (2013).
Language: English
Page range: 143 - 148
Submitted on: Sep 24, 2015
Published on: May 14, 2016
Published by: Slovak University of Technology
In partnership with: Paradigm Publishing Services
Publication frequency: 6 times per year
Keywords:
Related subjects:
© 2016 Marijan Jurgo, Romualdas Navickas, published by Slovak University of Technology
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.