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Note on Modular Reduction in Extended Finite Fields and Polynomial Rings for Simple Hardware Cover

Note on Modular Reduction in Extended Finite Fields and Polynomial Rings for Simple Hardware

By: Marek Repka  
Open Access
|Mar 2016

References

  1. [1] PATTERSON, N. J. : The Algebraic Decoding of Goppa Codes, IEEE Trans. on Information Theory 21 No. 2 (2012), 203–207.
  2. [2] FARKASOVA, K.—FARKAS, P.—RAKUS, M.—RUZICKY, E.—SILVA, A.—GAMEIRO, A. : Construction of Error Control Run Length Limited Codes Exploiting Some Parity Matrix Properties, Journal of Electrical Engineering 66 No. 3 (2015), 182–184.10.2478/jee-2015-0030
  3. [3] MALI, M.—NOVAK, F.—BIASIZZO, A. : Hardware Implementation of AES Algorithm, Journal of Electrical Engineering 56 No. 9-10 (2005,), 265–269.
  4. [4] RAKUS, M.—FARKAS, P. : Double Error Correcting Codes with Improved Code Rates, Journal of Electrical Engineering 55 No. 3-4 (2004,), 89–94.
  5. [5] EGOROV, S.—MARKARIAN, G. : Error Correction beyond the Conventional Error Bound for Reed-Solomon Codes, Journal of Electrical Engineering 54 No. 11-12 (2003), 305=-310.
  6. [6] RAKUS, M. : Comments on Weight Distribution of some Weighted Sum Codes for Erasure Correction, Journal of Electrical Engineering 53 No. 5-6 (2002), 138–142.
  7. [7] HEYSE, S.—GÜNEYSU, T. : Towards One Cycle per Bit Asymmetric Encryption: Code-Based Cryptography on Reconfigurable Hardware, CHES (2012), 340–355.10.1007/978-3-642-33027-8_20
  8. [8] SHOUFAN, A.—WINK, T.—MOLTER, H. G.—HUSS, S. A.—KOHNERT, E. : A Novel Cryptoprocessor Architecture for the McEliece Public-Key Cryptosystem, IEEE Trans. Computers 59 No. 11 (2010), 1533–1546.10.1109/TC.2010.115
  9. [9] BERNSTEIN, D. J.—LANGE, T.—PETERS, C. : Wild McEliece Incognito, 4th International Workshop, PQCrypto 2011, Proceedings, 2011, pp. 244–254.10.1007/978-3-642-25405-5_16
  10. [10] REPKA, M. : McEliece PKC Calculator, Journal of Electrical Engineering 65, No. 6 (2014), http://iris.elf.stuba.sk/JEEEC/data/pdf/6_114-03.pdf.10.2478/jee-2014-0056
  11. [11] REPKA, M.—CAYREL, P.-L. : Cryptography Based on Error Correcting Codes: A Survey, Multidisciplinary Perspectives in Cryptology and Information Security (Sattar B. Sadkhan Al Maliky, and Nidaa A. Abaas, ed.), IGI Global, 2014, pp. 133-156.10.4018/978-1-4666-5808-0.ch005
  12. [12] AN, H.-K. : Fast and Low cost GF(28) Multiplier Design based on Double Subfield Transformation, International Journal of Software Engineering and Its Applications 7 No. 4 (2013), 285–294.
  13. [13] CHUANPENG, CH.—ZHONGPING, Q. : Fast Algorithm and Hardware Architecture for Modular Inversion in GF(p), Intelligent Networks and Intelligent Systems, 2009. ICINIS ’09. Second International Conference on, 43-45, DOI: 10.1109/ICINIS.2009.20.10.1109/ICINIS.2009.20
  14. [14] MELIKOVIC, N. Z.—STANKOVIC, V.—MILIC, M. L. : Modular Design of Fast Leading Zeros Counting Circuit, Journal of Electrical Engineering 66 No. 6 (2015), 329–333.
DOI: https://doi.org/10.1515/jee-2016-0008 | Journal eISSN: 1339-309X | Journal ISSN: 1335-3632
Language: English
Page range: 56 - 60
Submitted on: Oct 8, 2015
Published on: Mar 17, 2016
Published by: Slovak University of Technology in Bratislava
In partnership with: Paradigm Publishing Services
Publication frequency: 6 issues per year

© 2016 Marek Repka, published by Slovak University of Technology in Bratislava
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 3.0 License.