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Area–Oriented Technology Mapping for LUT–Based Logic Blocks Cover

Area–Oriented Technology Mapping for LUT–Based Logic Blocks

International Journal of Applied Mathematics and Computer Science
Volume 27 (2017): Issue 1 (March 2017)
By: Marcin Kubica and  Dariusz Kania  
Open Access
|May 2017

Authors

Marcin Kubica

mkinz@wp.pl

Faculty of Mechanical Engineering and Computer Science University of Bielsko-Biała, ul. Willowa 2, 43-309, Bielsko-Biała, Poland

Dariusz Kania

dkania@polsl.pl

Institute of Electronics Silesian University of Technology, ul. Akademicka 2A, 44-100, Gliwice, Poland
DOI: https://doi.org/10.1515/amcs-2017-0015 | Journal eISSN: 2083-8492 | Journal ISSN: 1641-876X
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Language: English
Page range: 207 - 222
Submitted on: Oct 6, 2015
Accepted on: Oct 24, 2016
Published on: May 4, 2017
Published by: University of Zielona Góra
In partnership with: Paradigm Publishing Services
Publication frequency: 4 issues per year
Keywords:
SMTBDD,
FPGA,
synthesis,
decomposition
Related subjects:
Mathematics,
Applied mathematics

© 2017 Marcin Kubica, Dariusz Kania, published by University of Zielona Góra
This work is licensed under the Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 License.

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